“…(a) Many proposed circuitries (except FPAA, FPGA-based) have quite complex topology, with many active and/or passive elements [9,12,[16][17][18][19], especially circuits with fractional-order behavior and approximations by higher-order filters [3,5,6,13] or chain of bilinear segments [8,9,14,15,[18][19][20][21], (b) some concepts require software programming [12,16,17], (c) tested operational bandwidth is quite narrow in many cases [3][4][5]7,8,[11][12][13]18], (d) summing of fractional-order as well as integer-order two ports was not analyzed deeply in the past, (e) single-parameter electronic adjustment of the time constant of the resulting response of two-port summing was not studied in the past, except R. Sotner et al [9], but the overall circuit topology is based upon a chain of bilinear sections, and therefore, it is not one of the simplest solutions…”