Analog placement based on hierarchical module clustering

Lin, Po-Hung; Lin, Shyh-Chang

doi:10.1145/1391469.1391484

Cited by 39 publications

(15 citation statements)

References 14 publications

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“…The layout design hierarchy may contain both exact and virtual hierarchies of analog circuit design. The exact hierarchy is the same as the circuit hierarchy, while the virtual hierarchy consists of hierarchical clusters [17]. Each cluster contains some devices and sub-circuits which are gathered based on device models, sub-circuit functionality [9], [21], and/or other specific constraints [6].…”

Section: Hierarchical Placement With Layout Constraintsmentioning

confidence: 99%

“…2, it is essential to synthesize analog layout hierarchically for better efficiency and effectiveness. Modern analog placement techniques often simultaneously optimize the placement in different hierarchical sub-circuits, e.g., [18], [16], [17], [19], [25], instead of bottom-up integration, because the optimal placement of a subcircuit may not lead to the globally optimal placement. Most of them apply simulated annealing [12] based on the topological floorplan representations, such as sequence-pair [22] and B * -tree [5], while the latest one [25] adopts a full deterministic approach which will be introduced in Section IV.…”

Section: B Hierarchical Analog Placementmentioning

confidence: 99%

“…Section III presents hierarchical placement with layout constraints [17]. Hierarchy is applied as a means to further reduce the search space and leads to complex symmetry constraints across different levels of hierarchy.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analog layout synthesis - Recent advances in topological approaches

Graeb

Balasa

Castro-López

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

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Section: Hierarchical Placement With Layout Constraintsmentioning

confidence: 99%

Section: B Hierarchical Analog Placementmentioning

confidence: 99%

See 1 more Smart Citation

Analog layout synthesis - Recent advances in topological approaches

Graeb

Balasa

Castro-López

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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show abstract

“…Figure 4 shows a symmetric placement and its corresponding HB*-tree and ASF-B*-tree. Each module node, ni, corresponds to a module bi, and the hierarchy node nS0 corresponds to the symmetry island of the symmetry group S0 containing a selfsymmetric module, b In addition to handling symmetry constraints, the HB*-trees can also be hierarchically constructed based on the hierarchical circuit clustering [9] so that the close proximity of devices in the same sub-circuit is preserved during placement. For example, we can use different HB*-trees to model the device placements in different sub-circuits such as those in Figure 1.…”

Section: Thermal-driven Analog Placementmentioning

confidence: 99%

Thermal-driven analog placement considering device matching

Lin

Wong

Chang

2009

Proceedings of the 46th Annual Design Automation Conference

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With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers the desired placement configuration between power and thermally-sensitive devices for a better thermal profile to reduce the thermally-induced mismatches. In this paper, we first introduce the properties of a desired thermal profile for better thermal matching of the matched devices. We then propose a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints. Experimental results based on real analog circuits show that our approach can achieve the best analog circuit performance/accuracy with the least impact due to the thermal gradient, among existing works.

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“…Consequently, the top-level symmetry group S Top contains all device modules and other symmetry groups hierarchically. Based on the proposed symmetry-island and tree formulations, a hierarchical tree structure [24] that mixes both the ASF-B * -trees and the HB * -trees can be constructed. The optimized fully symmetric placement with the hierarchical symmetry constraint can then be obtained by searching a desired configuration of the tree structure and packing the trees to form the symmetry islands hierarchically.…”

Section: ) Multiple Symmetry-group Alignmentmentioning

confidence: 99%

Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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Analog placement based on hierarchical module clustering

Cited by 39 publications

References 14 publications

Analog layout synthesis - Recent advances in topological approaches

Analog layout synthesis - Recent advances in topological approaches

Thermal-driven analog placement considering device matching

Analog Placement Based on Symmetry-Island Formulation

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