Thermal-driven analog placement considering device matching

Abstract

With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers the desired placement configuration between power and thermally-sensitive devices for a better thermal profile to reduce the thermally-induced mismatches. In this paper, we first introduce the properties of a desired thermal profile for better thermal matching of the matched devices. We then propose a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints. Experimental results based on real analog circuits show that our approach can achieve the best analog circuit performance/accuracy with the least impact due to the thermal gradient, among existing works.

Performance-driven analog placement considering monotonic current paths

“…For the symmetry constraints, the symmetric-feasible conditions have been extensively studied in many topological representations, including sequence pairs (SP) [1], O-trees [10], binary trees [2], transitive closure graphs (TCG) [4], corner block lists (CBL) [8], and B*-trees [6]. In addition to the symmetry constraint, many other analog or general placement constraints, including boundary, commoncentroid, minimum/maximum-distance, pre-placement, proximity/range, regularity, symmetry-island, and thermal constraints, were also investigated in the recent works [3,5,6,7,8,9,11,14,12] 1 using the B*-tree, CBL, and SP representations, which are summarized in Table 1. During placement optimization, most of the recent works applied the simulated annealing algorithm [15], except [11] which is based on a non-stochastic approach.…”

“…Although modern analog placement algorithms [1,2,3,4,5,6,7,8,9,10,11,12] aimed to minimize area and wirelength under symmetry, proximity, and other topological constraints among devices during placement optimization, the generated layouts still may not meet the required circuit performance. It is because these algorithms failed to consider current/signal paths among devices, and the parasitics on the current/signal paths usually have the greatest impact Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Routability-driven placement algorithm for analog integrated circuits

“…To deal with the symmetry constraint, symmetric-feasible conditions have been explored for several representations, such as sequence-pairs [5], O-trees [6], binary trees [7], TCG [8], CBL [9], and B*-trees [10]. The placement algorithms based on CBL [9] and HB*-trees [11] further considered thermal effect with the symmetry constraint. Ma et al [12] and Xiao et al [13] handled the common-centroid constraint by C-CBL and sequence-pairs respectively.…”

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

“…Since their common-centroid placement results were based on a linear oxide gradient model, quadratic gradient errors were not taken into account. Lin et al [26] presented a thermal-driven placement algorithm for common-centroid placement considering thermal gradient, which is a kind of quadratic gradient [4]. However, their placements did not take account of device correlation for yield enhancement.…”