An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

Noda, K.; Takeda, Koichi; Matsui, K.; Masuoka, S.; Kawamoto, H.; Ikezawa, N.; Aimoto, Y.; Nakamura, N.; Iwasaki, Tadashi; Toyoshima, Hisashi; Horiuchi, T.

doi:10.1109/4.910490

Cited by 16 publications

(12 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A number of solutions, such as BL twisting, have been proposed to reduce cross talk noise and increase the signal-noise ratio (SNR) [Ohhata92,Noda01]. These solutions, however, focus mainly on overcoming BL coupling from a design point of view, in order to prevent data destruction during a write operation [Takeda00], or in order to reduce the BL delay time during the precharge cycle, thereby increasing overall memory performance [Nambu95].…”

Section: Effects Of Couplingmentioning

confidence: 99%

Evaluation of SRAM faulty behavior under bit line coupling

Al-Ars

Hamdioui

2008

2008 3rd International Design and Test Workshop

View full text Add to dashboard Cite

The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty behavior of SRAM devices. Spice simulations are used to show how coupling can prevent the detection of otherwise detectable faults. Furthermore, an evaluation is done of the needed bit line coupling conditions to guarantee a high fault coverage of a given defect. This is done by identifying the most stressful data background patterns in the neighborhood of the faulty cell.

show abstract

Section: Effects Of Couplingmentioning

confidence: 99%

Evaluation of SRAM faulty behavior under bit line coupling

Al-Ars

Hamdioui

2008

2008 3rd International Design and Test Workshop

View full text Add to dashboard Cite

show abstract

“…In fact, BL coupling and the resulting crosstalk noise is strongly considered as a limiting factor in designing high speed, low power SRAM devices [5]. Research on the impact of parasitic capacitance on the faulty behavior has up till now addressed faults in peripheral memory circuits as well as address decoders [14].A number of solutions, such as BL twisting, have been proposed to reduce cross talk noise and increase the signal-to-noise ratio [7], [8]. However, such solutions focus mainly on overcoming BL coupling from a design perspective and are expensive to implement making them infeasible in many applications [9], [6].…”

Section: Introductionmentioning

confidence: 99%

Bit line coupling memory tests for single-cell fails in SRAMs

Irobi

Al-Ars

Hamdioui

2010

2010 28th VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper evaluates the impact of bit line coupling in SRAMs on cell faulty behavior and identifies necessary conditions to induce worst-case coupling effects.We present a test that guarantees detecting all singlecell static faults in the presence of capacitive coupling and worst-case neighborhood data for any possible open defect.

show abstract

“…Typically, the amount of coupling noise between bitlines in diffusion-programming ROMs and other memories (SRAM, DRAM, Flash) is independent of the content on a column for a given memory configuration. These nonvaried coupling noises in other memories can be overcome by twisted bitline scheme [2], [3], open/fold bitline scheme [4], multiplayer shielded bitline structure [5], or ground-shielded open-bitline sensing scheme [6]. Unfortunately, various ROM code-patterns produce large variation of coupling noise between bitlines in contact and via-programming ROMs.…”

Section: Introductionmentioning

confidence: 99%

A Full Code-Patterns Coverage High-Speed Embedded ROM Using Dynamic Virtual Guardian Technique

Chang

Chiou

Wen³

2006

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Crosstalk between bitlines induces read failure and limits the coverage of applicable code-patterns for high-speed contact/via-programming read-only memories (ROMs) in SoC. Owing to the variation in bitline loading across code-patterns, the amount of coupled noise on an accessed bitline is code-pattern-dependent. This crosstalk effect worsens, with larger coupling capacitance and smaller intrinsic loading, as the technology node shrinks. This study proposes dynamic virtual guardian (DVG) techniques for contact/via-programming ROM macros and compilers to eliminate the crosstalk-induced read failure and increase the code-patterns coverage. Compared with conventional ROMs, DVG techniques achieve higher speed, lower power consumption and better design for manufacturing (DFM) capability with full code-patterns coverage. Experiments on fabricated designs, a conventional ROM and two 256 Kb DVG ROMs, using 0.18 m 1P5M CMOS technology have demonstrated that DVG techniques achieve 100% code-pattern coverage under a small sensing margin.

show abstract

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

Cited by 16 publications

References 5 publications

Evaluation of SRAM faulty behavior under bit line coupling

Evaluation of SRAM faulty behavior under bit line coupling

Bit line coupling memory tests for single-cell fails in SRAMs

A Full Code-Patterns Coverage High-Speed Embedded ROM Using Dynamic Virtual Guardian Technique

Contact Info

Product

Resources

About