An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

Zhou, Jun; Wang, Chao; Liu, Xin; Zhang, Xin; Je, Minkyu

doi:10.1109/tcsi.2014.2380691

Cited by 76 publications

(68 citation statements)

References 19 publications

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“…Most of the existing voltage level shifters are classified based on two topologies: Cross Coupled PMOS based (Type I) and Current Mirror based (Type II) [5].…”

Section: Level Shifter Circuitsmentioning

confidence: 99%

Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror

Parimala

Priyanka

Kaumudi

et al. 2015

2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

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___ In this paper, we present a Modified Revised Wilson Current Mirror Level Shifter (MRWCMLS) to convert subthreshold voltage to supply voltage with low leakage power. Increasing speed and complexity of today's designs resulted in increase in power consumption. System on Chip (SoC) may have few modules which are supplied with subthreshold voltage to achieve low power consumption and the remaining work with above threshold voltage supply. The level shifter which can convert subthreshold voltage level to supply voltage level is designed to minimize circuit leakage power with optimum number of transistors in the circuit. MRWCMLS has been implemented in 180 nm CMOS technology and is simulated using Cadence Virtuoso Simulator and the results are compared with the existing level shifters. In comparison with Revised Wilson Current Mirror Level Shifter (RWCMLS), the leakage power with normal transistors and with high Vth transistors type of implementation of the proposed MRWCMLS, is reduced by 34% and 43% respectively.

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“…Most of the existing voltage level shifters are classified based on two topologies: Cross Coupled PMOS based (Type I) and Current Mirror based (Type II) [5].…”

Section: Level Shifter Circuitsmentioning

confidence: 99%

Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror

Parimala

Priyanka

Kaumudi

et al. 2015

2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

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“…Moreover, it has a negative impact on overall power consumption. To address the design issue, few other designs are presented in the literature [18][19][20][21][22]. Among these solutions, level shifter circuits designed in [18,19,21] depend on the difference of voltage supply.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

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Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

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“…It is widely used in multi-rail power supply on-chip systems, such as Very Large Scale Integration circuit (VLSI), Micro-Electro-Mechanical Systems (MEMS), mixed-signal integrated circuits and power-conversion systems [1][2][3][4][5][6][7][9][10][11][14][15][16][17][18][20][21][22][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

“…For low voltage applications [3,10,20,25,26], with the supply voltage of logic circuit decreasing to subthreshold while the supply voltage of analog circuit remains unchanged, level shifter comes across new challenges [3]. The conventional level shifter design based on differential cascode voltage switch topology is limited for robust up-conversion from sub-threshold to super-threshold.…”

Section: Introductionmentioning

confidence: 99%

“…This is due to the significant current contention caused by the limited driving strength of the pull-down devices operating in the sub-threshold region. The existing methods to solve this problem are, (a) decreasing the driving strength of pull-up devices by adding current limitation structures [20] or increasing the driving strength of pull-down devices by reducing threshold [20]; (b) converting the sub-threshold signal to the superthreshold signal by a boosting capacitor [10]; (c) employing a differential amplifier to take advantage of its high voltage gain instead of traditional differential cascode voltage switch structures [26]. Other level shifter applications [1,9,21] include its use along with switch capacitor circuit to compensate operational amplifiers.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

Lai

Zhong

et al. 2017

Circuits Syst Signal Process

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In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module "inverse Schmitt trigger" to drive the pull-up transistors of conventional HVLS. As a result, the "Miller Plateau" caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5μm high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.

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An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

Cited by 76 publications

References 19 publications

Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror

Subthreshold voltage to supply voltage level shifter using modified revised wilson current mirror

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

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