An Ultra-Low-Power 4.7mA-Rx 22.4mA-Tx Transceiver Circuit in 65-nm CMOS for M2M Satellite Communications

Ouvry, Laurent; Lachartre, D.; Bernier, Carolynn; Lepin, Florent; Dehmas, François; Deslandes, Vincent

doi:10.1109/tcsii.2018.2820806

Cited by 9 publications

(11 citation statements)

References 5 publications

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“…Many modern wireless signal processing protocols require a high throughput implementation of the FFT algorithm. For example, this is true for the LoRa preamble detection algorithm presented above but also in satellite IoT detection algorithms [6]. When N is a power of 2, the FFT is an O(N logN ) algorithm to compute the N-point Discrete Fourier Transform (DFT) of the finite duration sequence x n and which is defined as:…”

Section: Fast Fourier Transform (Fft)mentioning

confidence: 99%

“…For example, authors in [2] and [3] use FPGA platforms to build agile cellular transceivers, from 3G to 5G. The recent development of small and nanosatellite systems has spurred interest in SDR for spaceborne multimode transceivers [4], [5], [6]. Closer to our application, authors in [7] propose a reconfigurable IoT gateway able to address the multiplicity of IoT communication standards.…”

Section: Introductionmentioning

confidence: 99%

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A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

Amor

Bernier

Přikryl³

2022

IEEE Trans. Comput.

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This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to come at a near-zero energy cost. Both an instruction accurate (IA) and a cycle accurate (CA) model of the new architecture are used to evaluate six IoT baseband processing test benches including FSK demodulation and LoRa preamble detection. Simulation results show cycle count improvements from 19% to 68%. Post synthesis simulations for a target 22nm FD-SOI technology show less than 1% power and 28% area overheads, respectively, relative to a baseline RV32IM design. Power simulations show a peak power consumption of 380 µW for Bluetooth LE demodulation and 225 µW for LoRa preamble detection (BW = 500 kHz, SF = 11).

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Section: Fast Fourier Transform (Fft)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

Amor

Bernier

Přikryl³

2022

IEEE Trans. Comput.

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“…The calculated admittances of the proposed compact-size tunable gain-equalizer topology are presented in (3) and (4). The Y-parameters of the conventional topology can be expressed as (5), and the S-parameters derived from the Yparameters were presented in (6) and (7).…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…The modern phased-array RADAR systems consist of several thousands of T/R modules, therefore; manufacturing costs, size, and integrability are important specifications for a T/R module. Recent advances and continued progress in the SiGe HBT BiCMOS technology have made it possible to build low-cost and fully-integrated compact size T/R modules with a competitive, sometimes even better, radio frequency (RF) performance compared to III-V counterparts [1]- [4].…”

Section: Introductionmentioning

confidence: 99%

A Tunable SiGe BiCMOS Gain-Equalizer For X-Band Phased-Array RADAR Applications

Turkmen

Burak

Ozkan

et al. 2019

IEEE Trans. Circuits Syst. II

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This paper presents a compact-size tunable gainequalizer for X-Band Phased-Array RADAR applications in a 0.25µm SiGe BiCMOS technology. An isolated NMOS based variable resistance was used for the first time to tune the slope of the gain-equalizer. For NMOS, an isolated body created by a deep n-well was utilized to reduce insertion loss due to the substrate conductivity. Furthermore, the power-handling capability of the tunable gain-equalizer was improved thanks to the resistive bodyfloating technique. The designed tunable gain-equalizer operates in the frequency range from 8 to 12.5 GHz with a measured positive slope of 1 dB/GHz and 1 dB tunable slope. The effective chip area excluding the pads is 0.21 mm 2 , and the total area including pads is 0.31 mm 2. To authors best knowledge, this study is the first tunable gain-equalizer in SiGe technology presented for X-band phased-array RADAR applications.

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“…Since the number of T/R modules is high, manufacturing costs, size, and integrability are important specifications for these modules. In SiGe HBT technology, thanks to the recent advances and progress in the SiGe technology, low-cost, fully-integrated compact size T/R modules with a competitive, sometimes even better, radio frequency(RF) performance compared to III-V counterparts have been published, recently [1]- [4].…”

Section: Introductionmentioning

confidence: 99%

A 7-Bit Reverse-Saturated SiGe HBT Discrete Gain Step Attenuator

Davulcu

Burak

Gürbüz

2020

IEEE Trans. Circuits Syst. II

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In this study, the analysis, design and measured results of a fully integrated 7-Bit step attenuator implemented in a 0.25-µm Silicon-Germanium (SiGe) BiCMOS process technology, are described. The attenuator is designed based on delicately ordered and cascaded Π/T type attenuation blocks, which are comprised of series/shunt switches employing SiGe hetero-junction bipolar transistors (HBTs) with peak fT /fmax of 110/180 GHz. HBTs are employed as a series switch to decrease the insertion-loss of the attenuator. Moreover, to authors' best knowledge, this is the first study presenting the effect of employing reverse-saturated HBTs as a shunt switch for each attenuation blocks. Thanks to this advancement, the highest input-referred 1-dB compression point (IP 1dB ) is reported for Si-based similar studies. This method also decreases the insertion-loss of the proposed attenuator. The measurements result in the state-ofthe-art performance with 28.575 dB attenuation range by 0.225 dB gain steps while maintaining 7-bit amplitude resolution across 6.6 GHz to 12.8 GHz frequency band, where RMS phase error remains below 3.3 • and insertion loss (IL) is less than 12.4 dB. The measured IP 1dB of the attenuator is 13.5 dBm while drawing 8 mA from 3.3 V supply. The die occupies an area of 1.37 mm x 0.56 mm excluding pads.

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An Ultra-Low-Power 4.7mA-Rx 22.4mA-Tx Transceiver Circuit in 65-nm CMOS for M2M Satellite Communications

Cited by 9 publications

References 5 publications

A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

A Tunable SiGe BiCMOS Gain-Equalizer For X-Band Phased-Array RADAR Applications

A 7-Bit Reverse-Saturated SiGe HBT Discrete Gain Step Attenuator

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