An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4

Bernier, Carolynn; Hameau, Frédéric; Billiot, G.; Foucauld, Emeric de; Robinet, S.; Durupt, Jean; Dehmas, François; Mercier, Éric; Vincent, Pierre; Ouvry, Laurent; Lattard, Didier; Gary, M.; Bour, C.; Prouvee, J.; Dumas, S.

doi:10.1109/rfic.2008.4561434

Cited by 9 publications

(11 citation statements)

References 5 publications

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“…The power consumption is controllable from 2.2 mW down to 0.7 mW. This is comparable with the state-of-the-art for this application, and further improvement may not be meaningful given the power consumption requirements of other blocks such as the frequency synthesizer; to our knowledge, the lowest power 2.4-GHz frequency synthesizer for IEEE 802.15.4 standard applications uses 2.4 mW [25]. The IIP 3 in the proposed design is also well within specifications, despite the use of an un-linearized IF section, and is comparable with recent literature.…”

Section: Comparisonmentioning

confidence: 85%

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

Aaron¹,

Boon

Anh

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract.A simple method to tune the output pole of a passive mixer is proposed which leads to up to 33 dB improvement in an IEEE 802.15.4 standard compatible receiver's IF section IIP 3 . This method is used in the design of an ultra-low power receiver front-end which consumes just 2.2 mW from a 1-V supply while achieving a SSB NF of approximately 9 dB. The energy-aware architecture allows for a 70 % reduction in the nominal power consumption (down to 0.7 mW) under strong signal conditions while improving the receiver's IIP 3 and not affecting the receiver's input matching. The receiver is designed in a 0.18-μm RFCMOS technology.

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Section: Comparisonmentioning

confidence: 85%

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

Aaron¹,

Boon

Anh

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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“…The measured result reveals that developing an ultra low-power EEG acquisition SOC is possible. To transmit the EEG signal through wireless communication, a 2.4 GHz fully integrated RF-transmitter with a merged PA and up- TABLE III SUMMARIZED PERFORMANCES OF THE PROPOSED RF FRONT-END OF THE TRANSMITTER AND ITS COMPARISON WITH PREVIOUSLY PUBLISHED STUDIES 2006 [14] 2007 [15] 2008 [16] 2009 [17] This work Power supply 1. specification. An SHIL-QVCO, with cross-coupled and current reuse topology, has also been proposed to provide the quadrature signals for I/Q modulation/demodulation.…”

Section: G Rf Front-end Of Receivermentioning

confidence: 99%

Wireless brain signal acquisition circuits for body sensor network

Lee

Hong

Wang

2012

2012 IEEE 11th International Conference on Cognitive Informatics and Cognitive Computing

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“…With additional RC section, damping factor reduces to slightly less than 1. The value of 3 R and 3 C are found to be 98. 32 shows the settling behavior of the synthesizer for fixed channel which shows the settling time is around 58 us.…”

mentioning

confidence: 90%

“…Here, the first stage divider is designed using current-mode logic (CML) [6] which consumes a large amount of power. The synthesizer reported in [3] consumes 2.4 mW at 1.2 V supply in 0.13 um CMOS technology. It uses a 16/17 dynamic logic prescaler as first stage divider which consumes only 176 uA at 2.5 GHz and the complete divider is designed with 5 MHz resolution.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

Krishna

Xie

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel Truesingle-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 uW. The S-QVCO consumes 2.8 mW of power with a phase noise of -122dBc/Hz at 1 MHz offset. IntroductionMost of the wireless communication standards prior to IEEE 802.15.4/Zigbee were tailored towards high data rate and multimedia friendly applications. The need for low data rate and low power wireless solutions with emphasis on sensor network applications resulted in the development of IEEE 802.15.4 standard. The recent development and advanced scaling CMOS technologies have made it more attractive to implement a single chip CMOS wireless transceiver featuring both high level of integration and low power consumption [1]. The higher power consumption in the frequency synthesizer is mainly due to the VCO and the first stage divider which is driven by the VCO. The 2.4 GHz synthesizer reported in [2] with a frequency resolution of 5 MHz consumes a power of 7.85 mW at 1.8 V power supply in 0.18 um CMOS technology. Here, the first stage divider is designed using current-mode logic (CML) [6] which consumes a large amount of power. The synthesizer reported in [3] consumes 2.4 mW at 1.2 V supply in 0.13 um CMOS technology. It uses a 16/17 dynamic logic prescaler as first stage divider which consumes only 176 uA at 2.5 GHz and the complete divider is designed with 5

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An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4

Cited by 9 publications

References 5 publications

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

Wireless brain signal acquisition circuits for body sensor network

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

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