A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

With the increasing demand for low cost and high integration of wireless transceiver building blocks, the low-power performance is a great concern for radio-frequency integrated circuit (RFIC) designers. Intensive effort has been made to develop RF integrated circuits and systems in the gigahertz range using the low-cost CMOS process. The commonly used frequency synthesizer based on the phase-locked loop (PLL) is an I would like to thank all the people who have made this thesis possible. First I would like to thank my advisor, Professor Do Manh Anh for his continuous guidance and support in the most difficult time of my graduate study. His kindly trust, constant encouragement, and pleasant personality have made my graduate study more enjoyable. I also would like to thank Assistant Professor Boon Chirn Chye and Professor Yeo Kiat Seng for giving me opportunity to work in RF group. I am greatly indebted and respectful for their encouragements and the kind support they have given me during the course work of my graduate study. I would like to extend my special thanks to Narendra Bolabattin, my advisor in IIIT Pune. I have learned a lot from him for analog circuit IC design. He has been a great advisor and a friend for me. I would like to thank my best friends Dr. Aaron Do, Dr. Lou Sha, Dr. Alper Cabuk and Dr. Ali Meaamar for their invaluable friendship. They were all there when it used to matter the most. I must acknowledge those numerous technical and personal discussions with them and thank them all for being my friends. I would like to thank Wei Meng Lim and T.S. Wong of RF group for assisting me in on-wafer measurement and testing. I also thank Ms. Xie Juan for valuable discussions on the design of voltage controlled oscillator. I would like to thank my lab mate Png Lih Chieh for his friendship and support. I would like to thank my dearest friend Ajay Nandagiri, for his important role v during my undergraduate study and his help in my life. He leaded me to the area of VLSI design. He was always been there with me during my difficult times and his encouragements supported me to finish my graduate study. I was also fortunate to have good friends during my MS study. Special thanks to Eapen Abraham, Ch.Kiran Kumar, Srinivas Chinta, Nishant Nukala and Bapaiah, for their accompanying through many difficult and delighted times.

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A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

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References 20 publications

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Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

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Ultra low power cmos phase-locked loop frequency synthesizers

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