An optimized pipelined architecture of SHA-256 hash function

Padhi, Meelu; Chaudhari, Ravindra

doi:10.1109/ised.2017.8303943

Cited by 25 publications

(15 citation statements)

References 8 publications

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“…On the Virtex 4 device, compared to that of the architectures in [19], [11], [10], and [21], the performance of our accelerator version 1-PE is 34 times, 1.6 times, 2.3 times, and 3.5 times better in terms of processing rate and 13.5 times, 1.4 times, 1.3 times, and 1.6 times better in terms of hardware efficiency, respectively.…”

Section: ) Fpga Synthesis Resultsmentioning

confidence: 94%

“…For instance, unrolled architectures [6], [7] were implemented to improve the processing rate in trade-offs with large areas and high power consumption. Pipelined architectures have been developed in many works, such as [8], [9], and [10], to increase the processing rate of the SHA-256 core. Furthermore, [8] employed the parallel counter technique to reduce the circuit area and critical path delay.…”

Section: Introductionmentioning

confidence: 99%

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A High-Performance Multimem SHA-256 Accelerator for Society 5.0

2021

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The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an applicationspecific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized 8.5mm × 8.5mm, consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

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Section: ) Fpga Synthesis Resultsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

2021

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“…Several optimizations of SHA-256 were recently published works. Some focused on optimizing SHA-256 hardware accelerator implementations for FPGA or ASIC by adopting pipelined architectures [16][17][18], while others adopted circuitlevel optimizations that shorten the critical path [19] or that reorder resource usage [20]. These works used a hardware description language (HDL) to implement the SHA-256 core and package it as an IP core [21].…”

Section: Related Workmentioning

confidence: 99%

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL

Bensalem

Blaquiere

Savaria

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The Secure Hash Algorithm-256 (SHA-256) is a cryptographic function used in a wide variety of applications ranging from Internet of Things micro-devices to highperformance systems. This paper studies a set of implementations of the SHA-256 on a field-programmable gate array (FPGA) elaborated using the Open Computing Language (OpenCL). These implementations apply several optimization techniques to improve their respective throughputs. Reported results show that a combination of OpenCL optimization techniques allows obtaining an implementation offering a 90x speed-up when compared to an unoptimized OpenCL implementation. Moreover, the best reported optimized implementation achieves a throughput of 3973 Mbps, which is 4.3 times higher than the best previously published HLS-based SHA-256 implementation and even higher than the previously published implementations using a hardware description language. To our knowledge, this work is the first that proposes an OpenCL-based FPGA implementation of SHA-256 and its OpenCL-based optimization methodology.

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“…Then, we calculate the processing rate for double SHA-256 (R d ) by using (10). The BlockSize is 1024 bits.…”

Section: ) Processing Rate and Hardware Efficiency Approachmentioning

confidence: 99%

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

et al. 2020

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In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18 µm technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5.9mm×5.9mm, and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

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An optimized pipelined architecture of SHA-256 hash function

Cited by 25 publications

References 8 publications

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

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