An on-line fault detection technique based on embedded debug features

Fault tolerant electronic system design

“…Debug infrastructures are intended to support software debugging in embedded system development, and are very common in modern processors. Since they are useless when the operational phase is entered, they can be easily reused for on-line monitoring in an inexpensive way [8,29,54,56]. On the other hand, they can provide internal access to the processor without disturbing it and do not require any modification either to the processor or to the software running on it.…”

“…The usage of debug infrastructures has been proposed as a way to increase the observability of soft errors with very limited latency, as presented in [29,54,56]. The technique proposed in this work follows the same approach, taking advantage of the already available features existing in many processors (standalone or cores) and using them to detect soft errors.…”

An Optical BILBO for Online Testing of Embedded Systems

“…As a matter of fact, techniques using COTS, such as duplication or triplication, are more often adopted [4], [23]- [25] since they have low error detection latency compared to other techniques described earlier. Moreover, the availability of low-cost COTS components in board-based systems, and the possibility of easily integrating a great amount of components in current SoCs are making hardware duplication a viable solution in many domains where system dependability is a major concern, even at the expense of extra area and power consumption [26].…”

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

“…• By resorting to the performance counters [10] existing in many processors and able to monitor the number of correctly/incorrectly executed predictions • By resorting to a timer able to measure the performance of the processor when executing a given piece of code, exploiting the fact that mispredictions imply longer execution time • By resorting to some debug feature provided by the processor [13] • By resorting to some ad-hoc module added to the system and able to monitor the bus activity [11].…”