An MTCMOS design methodology and its application to mobile computing

Abstract

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low V th transistors are used to implement the desired function, the high V th transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18 m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18 m process. The fabricated PDA processor operates at 333MHz, and consumes about 2 W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

“…This can be alleviated by employing an interface circuit with the capability of preserving the logic during standby mode. As storage elements lose their states in standby mode, alternative elements, which are capable of state retention, must be used [1], [4], [5]. Sizing of the current switch is critical in terms of performance, area, and leakage current [6].…”

Sleep transistor distribution in row-based MTCMOS designs

“…One of the most conservative approaches is the dedication of one ST to each logic cell and the optimization of individual STs, which is known as "fine-grained" leakage control [5] [6]. This approach makes it easier to do RT-level sign off by using standard static timing analysis techniques whereas it tends to incur large area overhead [7]. Other approaches [8] [9] group logic gates based on their current discharge patterns in a given switching cycle so that sleep transistors of gates with mutually exclusive current discharge patterns are merged together, thereby, reducing the area overhead.…”

“…This paper addresses the automatic placement of sleep transistors considering the interconnect resistance of the virtual ground in standard cell-based layout design. In [7] [16], the authors provide design methodologies that treat a ST as a standalone library cell and then calculate and allocate a number of sleep transistor cells (STCs) on each cell row. The STCs are then placed at one or the other corner of each row on a row-by-row basis.…”

Advanced NEMS-based power management for 3D Stacked Integrated Circuits

“…For certain specific low activity battery-operated embedded systems used in applications, e.g., environment monitoring sensors, biomedical implants, the sleep mode power, though having a low value, adds up to an energy figure that represents a significant fraction from the total energy consumed by the chip [4], [5]. For this reason new ways to further reduce the leakage power while mitigating the area and delay penalty are needed.…”