The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low V th transistors are used to implement the desired function, the high V th transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18 m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18 m process. The fabricated PDA processor operates at 333MHz, and consumes about 2 W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 m and a 0.080 m 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 with 200 mV improvement by NBL, and 0.47 for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

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A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and 10%, respectively, and the power consumption is reduced by 12% and 44%, respectively. Furthermore, the area of the SPSA is estimated to be 43% smaller than that of the ACSA. Although the SPSA has a 59% larger area than a dynamic pMOS sense amplifier, the area overhead can be mitigated by allocating a larger number of cells per bit-line (CpBL) because the performance of the SPSA is still better than that of the dynamic pMOS, even with a CpBL that is two times larger.Index Terms-AC-coupled sense amplifier, high-speed sensing amplifier, single-ended static RAM (SRAM), SRAM sensing.

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low V th transistors are used to implement the desired function, the high V th transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18 m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18 m process. The fabricated PDA processor operates at 333MHz, and consumes about 2 W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.