An MOS transistor charge model for VLSI design

Sheu, B.J.; Hsu, W.-J.; Ko, P.K.

doi:10.1109/43.3186

Cited by 35 publications

(6 citation statements)

References 19 publications

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“…The total Miller capacitance for a transistor can be as large as the total gate-oxide capacitance depending on the region the transistor is operating. The interested reader can refer to the \Introduction to Transcapacitance" and the BSIM \Charge-Based Capacitance Model" sections in the HSPICE User's Manual 14], and Sheu et al 16].…”

Section: Feedback Via Miller Capacitancementioning

confidence: 99%

Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits

Konuk

Ferguson

1998

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Shorts and opens are the most common types of catastrophic defects in today's CMOS ICs. In this paper we show that an open in the interconnect wiring of a digital CMOS circuit, which permanently disconnects inputs of logic gates from their driver, can cause oscillation or sequential behavior. We present supporting experimental data collected by creating an interconnect open in a manufactured chip. We also show that the conditions for oscillation and sequential behavior are likely to occur in many interconnect opens.

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Section: Feedback Via Miller Capacitancementioning

confidence: 99%

Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits

Konuk

Ferguson

1998

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…to fcnstores charge in the intrinsic, or channel, area of the transistor t when t is on [18]. Some charge is also stored on ds due to the gate overlap capacitance.…”

Section: Each Transistor Drain or Source Terminal Ds Connectedmentioning

confidence: 99%

Accurate and efficient fault simulation of realistic CMOS network breaks

Konuk

Ferguson

Larrabee

1995

Proceedings of the 32nd ACM/IEEE Conference on Design Automation Conference - DAC '95

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W e present a new fault simulation algorithm for realistic break faults in the p-networks and n-networks of static CMOS cells. We show that Miller eects can invalidate a test just as charge sharing can, and we present a new charge-based approach that eciently and accurately predicts the worst case eects of Miller capacitances and charge sharing together. Results on running our fault simulator on ISCAS85 benchmark circuits are provided. the broken paths in the p-network and no other path. Activating a path means applying ON voltages to the gates of all the transistors on the path. The second vector will make the faulty cell output high impedance with GND as its initial

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“…1. Each transistor drain or source terminal ds connected to fcnstores charge in the intrinsic, or channel, area of the transistor t when t is on [18]. Some charge is also stored on ds due to the gate overlap capacitance.…”

Section: A Charge-based Approachmentioning

confidence: 99%