An LTPS active-matrix process with PECVD doped N[sup +] drain/source areas

Abstract

Abstract— A low‐temperature polysilicon active‐matrix process without the need for ion implantation to dope drain and source areas of TFTs has been developed. A doped silicon layer is deposited by PECVD and structured prior to the deposition of the intrinsic silicon for the channel. The dopant is diffused and activated during the excimer‐laser crystallization step. N‐channel test TFTs with different geometries were realized. The TFT properties (mobility, on/off ratio, saturation, etc.) are suitable to realize AMLCDs and AMOLED displays and to integrate driver electronics on the displays. In addition to simple TFTs, a full‐color 4‐in. quarter‐VGA AMLCD was realized. The complete display (including photolithographic masks, active‐matrix backplane, and color‐filter/black‐matrix frontplane), and an addressing system were developed and manufactured at the Chair of Display Technology, University of Stuttgart, Germany. The substitution of ion doping by PECVD deposition overcomes a major limitation for panel sizes in poly‐Si technology and avoids large investment costs for ion‐implantation equipment.

A five mask CMOS LTPS process with LDD and only one ion implantation step

“…Based on our ion-doping free process for NMOS LTPS TFTs, we have developed an LTPS (450 °C maximum process temperature) CMOS process that requires only five photolithographic steps [4]. The entire process flow is shown in Fig.…”

“…The TFTs showed the same performance as TFTs produced on SAELC-material with more complicated processes. The availability of ion doping free NMOS TFTs allows the implementation of large area active matrices, while an ion doping step is necessary only for the high performance driver electronics at the borders of the panel [4]. The throughput can be enhanced by reducing the time spent in the ion doping equipment.…”