A five mask CMOS LTPS process with LDD and only one ion implantation step

Schalberger, Patrick; Persidis, Efstathios; Fruehauf, Norbert

doi:10.1080/15980316.2007.9652018

Cited by 10 publications

(5 citation statements)

References 4 publications

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“…4 This requires another implantation step and often also a further lithographic step, which are not required in our process. Although our CMOS process was presented elsewhere, 5 a brief overview of the process will be given here for a comprehensive description of the implemented AMOLED. First, a buffer SiO 2 followed by highly phosphorous-doped silicon is deposited by PECVD.…”

Section: Ltps Processmentioning

confidence: 99%

A fully integrated 1‐in. AMOLED display using current feedback based on a five‐mask LTPS CMOS process

et al. 2011

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Abstract— In the past, a five‐mask LTPS CMOS process requiring only one single ion‐doping step was used. Based on that process, all necessary components for the realization of a fully integrated AMOLED display using a 3T1C current‐feedback pixel circuit has recently been developed. The integrated data driver is based on a newly developed LTPS operational amplifier, which does not require any compensation for Vth or mobility variations. Only one operational amplifier per column is used to perform digital‐to‐analog conversion as well as current control. In order to achieve high‐precision analog behavior, the operational amplifier is embedded in a switched capacitor network. In addition to circuit verification by simulation and analytic analysis, a 1‐in. fully integrated AMOLED demonstrator was successfully built. To the best of the authors' knowledge, this is the first implementation of a fully integrated AMOLED display with current feedback.

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Section: Ltps Processmentioning

confidence: 99%

A fully integrated 1‐in. AMOLED display using current feedback based on a five‐mask LTPS CMOS process

et al. 2011

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“…The p-channel metal oxide semiconductor (PMOS) architecture using LTPS TFT is preferred over n-channel metal oxide semiconductor (NMOS) TFT in display applications, because it is less likely to be influenced by the bias stress. [21][22][23][24][25] The mechanical stability of the TFT backplane is very important to realize the reliability of foldable AMOLED displays. Most of the small size mobile displays use LTPS TFT backplane; however, the mechanical stability remains a critical issue to be solved.…”

Section: Introductionmentioning

confidence: 99%

“…The p‐channel metal oxide semiconductor (PMOS) architecture using LTPS TFT is preferred over n‐channel metal oxide semiconductor (NMOS) TFT in display applications, because it is less likely to be influenced by the bias stress. [ 21–25 ]…”

Section: Introductionmentioning

confidence: 99%

Excellent Mechanical Durability of In‐Folding Stress of Poly‐Si Thin‐Film Transistor on Plastic Substrate Compared with Out‐Folding: Generation of Gate Leakage Currents in Flexible Poly‐Si Thin‐Film Transistor by Out‐Folding and Bias‐Temperature Stress

et al. 2020

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The effect of electro‐thermal stress on the electrical performance of flexible, low‐temperature polysilicon (LTPS) thin‐film transistors (TFTs) after mechanical‐folding stress aiming to improve the reliability of foldable display backplanes is studied (IG). Herein, for the first time, the significant increase of gate leakage currents upon the negative bias temperature stress (NBTS) or positive bias temperature stress (PBTS) after the out‐folding test on excimer laser annealing (ELA) TFTs is reported. Out‐folding stress increases the drain current, shifts the threshold voltage (ΔVTH) by 2.4 V, and increases the subthreshold swing without affecting the (IG). However, the ΔVTH is 1.8 V upon NBTS, and the negative ΔVTH is −4.7 V upon PBTS after out‐folding stress along with a drastic increase in IG. A thermal annealing at 250 °C for 10 h for the electro‐thermal stressed TFTs after out‐folding is performed, and initial electrical characteristics recovery is achieved; except the abruptly increased IG. These results are correlated with charge trapping at the damaged grain boundary and (GI). A model with moisture/water molecule diffusion through the nanocracks generated by out‐folding is proposed. The ionized charges (H+, OH−) captured at the nanocrack‐induced trap sites in poly‐Si and GI appear to be the origin of abnormal ΔVTH and IG.

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“…The shortcoming of their work is that metal is used as the storage electrode, which affects the aperture ratio. [5] Schalberger et al reported a five mask LTPS structure, which, however, did not have the indium tin oxide (ITO) layer for pixel electrode [6]. Accordingly, it is an incomplete structure for the proper operation of an LCD panel.…”

Section: Introductionmentioning

confidence: 99%

P‐52: A Novel Six‐Mask Low‐Temperature Polycrystalline Silicon Architecture for TFT‐LCD Application

Luo

He²,

Xu³

et al. 2020

Symp Digest of Tech Papers

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A novel six-mask LTPS TFT architecture is fabricated and used in TFT-LCD. The light shielding layer and organic layer are removed. Furthermore, the pixel indium tin oxide and source drain patterns are developed in one halftone mask. To solve the issue of high photo leakage current, we have investigated the generation mechanism of Iphoto and established guidelines for reducing it. The optical and electrical characteristics of the sixmask TFT-LCD are comparable to those of conventional TFT-LCD.

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A five mask CMOS LTPS process with LDD and only one ion implantation step

Cited by 10 publications

References 4 publications

A fully integrated 1‐in. AMOLED display using current feedback based on a five‐mask LTPS CMOS process

A fully integrated 1‐in. AMOLED display using current feedback based on a five‐mask LTPS CMOS process

Excellent Mechanical Durability of In‐Folding Stress of Poly‐Si Thin‐Film Transistor on Plastic Substrate Compared with Out‐Folding: Generation of Gate Leakage Currents in Flexible Poly‐Si Thin‐Film Transistor by Out‐Folding and Bias‐Temperature Stress

P‐52: A Novel Six‐Mask Low‐Temperature Polycrystalline Silicon Architecture for TFT‐LCD Application

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