An L-Shaped Trench SOI-LDMOS With Vertical and Lateral Dielectric Field Enhancement

A low specific on-resistance power trench MOSFET with a buried-interface-drain

“…A more uniform vertical electric field is obtained and V L2 in Fig. 2(a) is enhanced, and therefore, the V B is increased from 91 V to 133 V. Moreover, the maximum doping concentration in the n-drift region can be increased from 1.9 Â 10 14 cm À3 for the device without a p-silicon to 1.6 Â 10 16 cm À3 for the device with a p-silicon, which means a lower R on,sp at the [8] [4] [6] [2] ideal Si limit [22] Ron,sp (m cm [11] 107 0.96 11.9 ERT SOI pLDMOS in [16] 329 13. At the on-state, the introduced interface buried n + layer (low-resistance) for BID MOSFET shortens the distance between the channel and n + region at drain side compared with the conventional trench MOSFET, which will lead to a lower R on,sp just as shown in the inset of Fig.…”

“…In 2007, Varadarajan et al introduced trench-gate (vertical channel) into the conventional trench MOSFET and proposed double trenches power MOSFET, which exhibited a R on,sp of 7 mX cm 2 with a V B of 250 V [5], and almost meanwhile, 80V class double trenches MOSFETs with a planar drain or a plug drain were studied by them [6][7][8]. In 2011, trench power MOSFETs based silicon-on-insulator (SOI) were investigated by Xiaorong Luo [9,10], and after which, Zhigang Wang proposed a L-Shaped Trench SOI LDMOS in 2012 [11]. Orouji and Mehrad proposed an inserted P-layer in trench oxide (IPT-LDMOS) in [12].…”

High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

“…Conventionally, the dielectric filed (E I ) of the BOX can be expressed by equation ε I E I = ε Si E Si + qσ in [7]. E Si is the electric field of silicon at Si/SiO 2 interface, ε Si and ε I are the permittivity of the silicon and dielectric buried layer.…”

A 100-V High-Performance SOI Trench LDMOS with Low Cell Pitch

“…3 This trade-off between breakdown voltage (V br ) and specific on-resistance (R on,sp ) is quantified by Baliga's figure of merit (BFOM = V br 2 /R on,sp ), 4 which should be as high as possible. Moreover, for given on-resistance, the gateto-drain charge (Q gd ) should be minimized to improve the switching performance of an LDMOS, which is evaluated by the dynamic figure of merit (FOM = R on,sp AEQ gd ).…”