An investigation of the intrinsic delay (speed limit) in MTL/I/sup 2/L

Berger, H.H.; Helwig, Klaus

doi:10.1109/jssc.1979.1051182

Cited by 16 publications

(3 citation statements)

References 36 publications

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“…The parameters needed to satisfy the inverting action conditions were determined by two-dimensional (2-D) simulation (MEDICI) from which the SPICE dc model parameters were extracted. The results of this process [10] identified the importance of minimizing spreading resistance, particularly in the switch emitter, in addition to the requirements set by (2) and (3). The material parameters that are required to allow inverting action are given in Table I.…”

Section: B Sige I L Simulationsmentioning

confidence: 99%

“…Integrated injection logic or I L [1], [2] is a low power bipolar technology suitable for VLSI which traditionally has suffered from a relatively poor dynamic performance. The minimum gate delay of Si I L [3] is primarily determined by stored charge in parasitic diodes associated with the extrinsic base regions of the I L gate. Self-aligned collector-base structures have been reported [4] which minimize the area of these parasitic diodes and deliver a gate delay of 0.8 ns for a layout geometry of 2.5 m and a fan-out of 3.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of Si:Ge heterojunction integrated injection logic (I/sup 2/L) structures using a stored charge model

Wainwright

Hall

Ashburn

et al. 1998

IEEE Trans. Electron Devices

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A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I 2 L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I 2 L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I 2 L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NpN emitter layer. The inclusion of 16% Ge in the substrate-fed I 2 L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I 2 L even at a geometry of 3 m. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure. NOMENCLATURE N-type Si doping concentration in the substrate (used exclusively in C-I L). N-type Si doping concentration in the switch emitter (used exclusively in C-I L). N-type Si doping concentration in the injector base

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Section: B Sige I L Simulationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of Si:Ge heterojunction integrated injection logic (I/sup 2/L) structures using a stored charge model

Wainwright

Hall

Ashburn

et al. 1998

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…R ING oscillators are used extensively in analog/digital timing circuits [1][2][3][4], for the measurement of gate delays [5,6] and for realising VCOs. A ring oscillator is a very simple structure where the output of a serially connected odd number of inverters is fed back to the input.…”

mentioning

confidence: 99%