An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS

Zheng, Kevin; Frans, Yohan; Ambatipudi, Sai Lalith Chaitanya; Asuncion, Santiago; Reddy, Hari Teja; Chang, Ken; Murmann, Boris

doi:10.1109/vlsic.2018.8502377

Cited by 9 publications

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“…The fact that the gain can be distributed along the interleaving chain provides another degree of freedom for the receiver design, allowing a small received signal to be amplified to the full scale of the quantiser. Finally, two other design variables are present, the supply voltage and the device threshold voltage, since they both affect the circuit's bandwidth and linearity [5].…”

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confidence: 99%

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80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold

Mattia

Murmann

2020

Electron. lett.

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An inverter-based track-and-hold circuit that merges the functions of buffering and sampling is proposed, simultaneously improving linearity, bandwidth and power efficiency when compared to stateof-the-art designs. The circuit operation and its governing equations are presented, and simulation results of an 80 GS/s, 5.5 ENOB timeinterleaved prototype consuming 25 mW from a 0.7 V supply demonstrate the advantages of the proposed topology using a predictive 7 nm FinFET CMOS technology.

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“…The first rank shows DC gain of −0.6 dB and 57.9 GHz −3 dB bandwidth. A series resistance of 600 V was used to increase the stage's bandwidth, as in [5], while further peaking could be used to compensate for the packaging and input matching network limitations.…”

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confidence: 99%