An intra-chip free-space optical interconnect

Abstract

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra-and inter-chip interconnect technologies.Optical interconnect is a promising long term solution. However, while significant progress in optical signaling has been made in recent years, applying conventional packetswitching interconnect architecture to optical networks require repeated E/O and O/E conversions that significantly diminish the advantages of optical signaling. In this paper, we propose to leverage a suite of newly-developed or emerging devices, circuits, and optics technologies to build a fully distributed interconnect architecture based on free-space optics. With a complexity-effective communication support layer to manage occasional packet collisions, the interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.

Efficient multicast schemes for 3-D Networks-on-Chip

“…a separate layer, while the other tiles are composed of processors, L1 caches, and routers. For real benchmarks, the communication traces of two SPLASH-2 benchmarks [34], fft and ocean are extracted from the same simulator [33]. Based on the traffic analysis of the traces, two synthetic traffics are generated with the same injection rate, size and distribution of destinations, and MUR as those of the original trace files.…”

Enhancing effective throughput for transmission line-based bus

“…These proposals range from networks-on-chip (NoC) [5,19,24,35,38,43] to optical interconnects [16,23,30,31,40,42,45] or RF interconnects [6,[12][13][14]. Even with the use of circuitor device-level support for optics or RF circuitry, many designs still rely on packet-switching at the architecture level [6,[12][13][14]16].…”

A case for globally shared-medium on-chip interconnect

“…These proposals range from networks-on-chip (NoC) [7,23,38,43,50] to optical interconnects [22,30,31,47,53] or RF interconnects [8,[13][14][15]41]. Transmission line mechanisms have been explored by Beckmann and Wood to enhance the communication in L2 caches [8,9].…”

“…The two state machines combined handle a total of 13 transient states and 57 legal transistions (excluding deferred handling) [52].…”