An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Wang, Wenping; Reddy, V.; Krishnan, A.T.; Vattikonda, Rakesh; Krishnan, S.; Cao, Yu

doi:10.1109/cicc.2007.4405783

Cited by 32 publications

(68 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Today this phenomenon is becoming a major concern in analog and digital circuit design, due to the increasing electric fields in nanometer CMOS technologies [45], [12].…”

Section: Hot Carrier Injectionmentioning

confidence: 99%

Emerging yield and reliability challenges in nanometer CMOS technologies

Gielen

Wit

Maricau

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

View full text Add to dashboard Cite

With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.

show abstract

“…Today this phenomenon is becoming a major concern in analog and digital circuit design, due to the increasing electric fields in nanometer CMOS technologies [45], [12].…”

Section: Hot Carrier Injectionmentioning

confidence: 99%

Emerging yield and reliability challenges in nanometer CMOS technologies

Gielen

Wit

Maricau

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

View full text Add to dashboard Cite

show abstract

“…Based on the reaction-diffusion mechanism, real time NBTI model is developed in [21,22] shown in Table I.…”

Section: A Standby Time Aware Nbti Modelingmentioning

confidence: 99%

“…Recently, many researchers have studied the NBTI modeling and mitigation techniques on various design abstraction levels. Analytical compact models [6][7][8] that evaluate NBTI effects using power-law timing degradation were proposed to help designers estimate the performance degradation. Based on these transistor compact models, circuit level NBTI degradation analysis models were proposed [9,10].…”

Section: Introductionmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

Self Cite

View full text Add to dashboard Cite

Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

show abstract

“…On the other hand, power consumption due to power gating for recovery is also dependent on T h . We evaluated the worst V th shift using the NBTI long-term prediction model [5] assuming that all PMOSs in a cell are under stress when the cell is active. In TMR mode, stress phase remains for 3T h followed by recovery phase of T h .…”

Section: Aging Processmentioning

confidence: 99%

“…Once the stress is removed, the |V th | is partially recovered. Consequently, the ratio of stress and recovery phases and their frequency are found to be important factors to characterize NBTI [5]. Especially long-term stress, such as 10 seconds, heavily degrades performance.…”

Section: Introductionmentioning

confidence: 99%

Coarse-grained dynamically reconfigurable architecture with flexible reliability

Alnajiar

Imagawa

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.

show abstract

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Cited by 32 publications

References 10 publications

Emerging yield and reliability challenges in nanometer CMOS technologies

Emerging yield and reliability challenges in nanometer CMOS technologies

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Coarse-grained dynamically reconfigurable architecture with flexible reliability

Contact Info

Product

Resources

About