An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS

Kar, Monodeep; Singh, Arvind; Rajan, Anand Prem; De, Vivek; Mukhopadhyay, Saibal

doi:10.1109/esscirc.2016.7598339

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…However, it is specific for AES engines that use a fixed key. Noise injection and power isolation are other techniques that hide the intermediate values of encryption operations [17,22,25,26,48,49]. The authors of ANSI [17] combine these two techniques to implement a generic solution for encryption algorithms with negligible performance overhead.…”

Section: Power Analysis Attack Countermeasuresmentioning

confidence: 99%

Mitigating Power Attacks through Fine-Grained Instruction Reordering

Chen¹,

Hajiabadi²,

Poussier³

et al. 2021

Preprint

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Side-channel attacks are a security exploit that take advantage of information leakage. They use measurement and analysis of physical parameters to reverse engineer and extract secrets from a system. Power analysis attacks in particular, collect a set of power traces from a computing device and use statistical techniques to correlate this information with the attacked application data and source code. Countermeasures like just-in-time compilation, random code injection and instruction descheduling obfuscate the execution of instructions to reduce the security risk. Unfortunately, due to the randomness and excess instructions executed by these solutions, they introduce large overheads in performance, power and area.In this work we propose a scheduling algorithm that dynamically reorders instructions in an out-of-order processor to provide obfuscated execution and mitigate power analysis attacks with little-to-no effect on the performance, power or area of the processor. We exploit the time between operand availability of critical instructions (slack) to create high-performance random schedules without requiring additional instructions or static prescheduling. Further, we perform an extended security analysis using different attacks. We highlight the dangers of using incorrect adversarial assumptions, which can often lead to a false sense of security. In that regard, our advanced security metric demonstrates improvements of 34×, while our basic security evaluation shows results up to 261×. Moreover, our system achieves performance within 96% on average, of the baseline unprotected processor. * Yun Chen and Ali Hajiabadi contributed equally to this work.

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Section: Power Analysis Attack Countermeasuresmentioning

confidence: 99%

Mitigating Power Attacks through Fine-Grained Instruction Reordering

Chen¹,

Hajiabadi²,

Poussier³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…in [54] used air-core package inductance for realizing a high frequency power stage. Package bondwires offer relatively higher inductance value than on-chip inductance and have been used in inductive IVRs [49,52,53,43,61]. Recently published works report magnetic interposer [59], magnetic thin film [60], on-chip solenoid [55] and embedded magnetic core inductors [62] achieving higher inductance density than the traditional on-chip spiral or package inductors.…”

Section: Integration Of On-chip/on-package Inductancementioning

confidence: 99%

“…IVRs demonstrate fast recovery from voltage droops due to load current transients as well as fast switching from one reference voltage (corresponding to a power-state of the processor) to another reference voltage [41,1,42,35,43,44]. VRs, specifically switching VRs like inductive buck regulators [55,50] and SCVRs [42,36] require passives (inductors and capacitors) which typically are implemented as discrete PCB components for VRMs with low switching frequencies.…”

Section: Chapter 3 Modeling and Analysismentioning

confidence: 99%

“…Voltage regulators integrated into the same die as the digital logic, referred to as Integrated Voltage Regulators (IVRs) have been demonstrated to improve energy efficiency of digital processors [41,1,42,35,43,44,45,46,47]. Integration of voltage regulators achieve fast transitions of processor supply voltage between power-states which maximizes the benefits of DVFS and improves the transient response of supply voltage to dynamic load current transitions.…”

Section: Introductionmentioning

confidence: 99%

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