Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering

Singh, Arvind; Kar, Monodeep; Mathew, Sanu; Rajan, Anand Prem; De, Vivek; Mukhopadhyay, Saibal

doi:10.1109/esscirc.2017.8094523

Cited by 13 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It has been shown in this thesis that a security aware inductive IVR design, primarily meant for improving energy efficiency, can improve both power and EM side channel resistance. This thesis, along with few other recently published works [103,104,105] open up a new direction of research where circuit techniques for energy-efficiency can be used for improvement in side channel resistance.…”

Section: Future Directionsmentioning

confidence: 93%

“…New Attack Mode: LR is shown to be effective against existing statistical tests like CPA and TVLA (higher order TVLA for EMSCA). Other randomization based techniques like use of random fast voltage dithering in [105] have been recently proposed. The future research can focus on trying to find new attack modes for breaking any protection achieved through randomization of control loop or other elements in power delivery.…”

Section: Usage Of Integrated Inductancementioning

confidence: 99%

See 1 more Smart Citation

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Kar

Singh

Mathew

et al. 2016

Proceedings of the 2016 International Symposium on Low Power Electronics and Design

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Future Directionsmentioning

confidence: 93%

Section: Usage Of Integrated Inductancementioning

confidence: 99%

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Kar

Singh

Mathew

et al. 2016

Proceedings of the 2016 International Symposium on Low Power Electronics and Design

Self Cite

View full text Add to dashboard Cite

show abstract

“…The countermeasure closest to that proposed in this paper is dynamic voltage scaling (DVS). DVS affects both the timing and amplitude of power traces [1,20,23]. However, most DVS approaches have been restricted to using a single voltage for the entire design and are vulnerable to the estimation of the random voltage [1].…”

Section: Introductionmentioning

confidence: 99%

Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks

Chen,

Goins,

Waugaman

et al. 2023

Proceedings of the Great Lakes Symposium on VLSI 2023

View full text Add to dashboard Cite

In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power sidechannel attacks. We first analyze the impact of the number of independent voltage islands on the resulting signal-to-noise ratio and trace misalignment. As part of our analysis of misalignment, we propose a novel unsupervised machine learning (ML) based attack that is effective on systems with three or fewer independent voltages. Our results show that iRDVS with four voltage islands, however, cannot be broken with 200k encryption traces, suggesting that iRDVS can be effective. We finish the talk by describing an iRDVS test chip in a 12nm FinFet process that incorporates three variants of an AES-256 accelerator, all originating from the same RTL. This included a synchronous core, an asynchronous core with no protection, and a core employing the iRDVS technique using asynchronous logic. Lab measurements from the chips indicated that both unprotected variants failed the test vector leakage assessment (TVLA) security metric test, while the iRDVS was proven secure in a variety of configurations. CCS CONCEPTS• Security and privacy → Side-channel analysis and countermeasures; • Computing methodologies → Unsupervised learning.

show abstract

“…The threshold implementations of AES S-box usually take tens of cycles for one computation. Concerning the hiding methods, most of the equalization methods [7] or the noising methods [8] must consume extra energy as the compensation or noise component. Random voltage or clock dithering [9] has less overhead but its effectiveness will be decreased when enhanced alignment technique (e.g.…”

Section: Introductionmentioning

confidence: 99%

Side-channel attack-resistant AES S-box with hidden subfield inversion and glitch-free masking

Li¹,

Jiao²,

Yang³

2021

J. Semicond.

View full text Add to dashboard Cite

A side-channel attack (SCA)-resistant AES S-box implementation is proposed, which is an improvement from the power-aware hiding (PAH) S-box but with higher security and a smaller area. We use the composite field approach and apply the PAH method to the inversion in the nonlinear kernel and a masking method to the other parts. In addition, a delay-matched enable control technique is used to suppress glitches in the masked parts. The evaluation results show that its area is contracted to 63.3% of the full PAH S-box, and its power-delay product is much lower than that of the masking implementation. The leakage assessment using simulation power traces concludes that it has no detectable leakage under t-test and that it at least can thwart the moment-correlation analysis using 665 000 noiseless traces.

show abstract

Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering

Cited by 13 publications

References 12 publications

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks

Side-channel attack-resistant AES S-box with hidden subfield inversion and glitch-free masking

Contact Info

Product

Resources

About