An integrated-circuit reliability simulator-RELY

Compact modeling for simulation of circuit reliability: Historical and industrial perspectives

“…However, this name was already taken by the hot-carrier degradation simulator developed at USC [31]. We thus put our heads together, thinking of some acronym related to reliability, but we believe it was one of the professors which came up with something completely different, BERT (BErkeley Reliability Tools).…”

Design considerations for CMOS digital circuits with improved hot-carrier reliability

“…In digital logic circuits, the degradation of the MOS current-voltage characteristics is attributed primarily to the generation of interface traps near the drain [7], [9]. The time-dependent increase of the interface trap density can be described as a simple function of the average bond-breaking current density over one period [5], [6]. The bond-breaking current density is defined as , where and represent the drain current and the substrate current, respectively, and represents the channel width of the MOS transistor.…”

“…In an MOS transistor experiencing hot-carrier induced degradation, the linear region drain current exhibits a much more pronounced decrease than the saturation region current [2]. The amount of current degradation in the linear operating region can be shown to be proportional to the generated interface trap density near the drain (5) For simplicity, this current degradation can be attributed to a proportional decrease in the MOS transconductance as follows, where represents an empirical proportionality factor (6) In the saturation region, on the other hand, the current degradation will be assumed to be negligible. This assumption greatly simplifies the analysis of transient performance degradation in CMOS inverter circuits while preserving the accuracy of the degradation model.…”

Explicit geometry dependence of MOS transistor parameters by the pseudoboundary method

“…It serves as an essential link between the process/device development effort and the chip design effort of VLSI production. The circuit level simulator [5], [6] provides information to higher level simulators, such as the timing simulator [7] and reliability simulator [8], based on information from more detailed device and process simulators [9], [10]. The ability of circuit designers to satisfy the specifications imposed upon them and make the best use of the available technology is highly dependent on the circuit simulation capability at their disposal.…”