An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

Barman, Kuheli Roy; Baishya, Srimanta

doi:10.1007/s00339-019-3165-9

Cited by 17 publications

(10 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Figure 10(b) depicts the effect of gs and ox on LG variation with respect to VGS at VDS = 0.7 V. The parasitic capacitance gs and intrinsic capacitance ox decreases with LG scaling [18]. The device exhibits gs of 0.2 fF at LG = 5 nm and 0.1 fF which is 5x times increment.…”

Section: Results Analysismentioning

confidence: 99%

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

Sreenivasulu

Narendar

2021

Preprint

View full text Add to dashboard Cite

We demonstrate junctionless (JL) n-channel SOI nanowire FET with asymmetric spacer at nano regime. The impact of various spacer dielectrics on device performance is presented and various electrical characteristics are analyzed. The gate length (LG) scaling impact of the asymmetric spacer with various spacers on ION, IOFF, and ION/IOFF is analyzed. The device exhibits excellent electrical characteristics with SS = 64 mV/dec, DIBL = 45 mV/V, ION/IOFF = 106 even at 5 nm LG ensures better electrostatic integrity. From the result analysis it is noted that spacer plays a detrimental role in reducing OFF current (IOFF) at lower LG. Moreover, the power analysis on scaling with various spacer dielectrics is performed. The analog/RF performance is also performed and scaling feasibility with HfO2 spacer is presented. The result analysis ensures asymmetric JL nanowire FET is one of the possible options to continue scaling.

show abstract

Section: Results Analysismentioning

confidence: 99%

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

Sreenivasulu

Narendar

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…9,10 In addition, since the carrier transport is primarily controlled by a single gate, carrier mobility improves for lower body thickness in a VSTB FET. 10,11 Hence, I on also enhances. Besides, the fabrication of this new device is much simpler than SOI FETs.…”

Section: Introductionmentioning

confidence: 95%

“…These extremely thin fins, lacking mechanical strength, can be broken or washed away anytime during the cleaning process by the sonication method. [7][8][9][10][11][12] All these challenges encountered with these novel devices encourage further innovation of the device structure. From this perspective, Koldyaev and Pirogova introduced a new single gate structure called vertical super-thin body (VSTB) FET, in which a semiconducting low doped VSTB is constituted on a dielectric wall, such as the shallow-trench isolation (STI) wall.…”

Section: Introductionmentioning

confidence: 99%

The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

Self Cite

View full text Add to dashboard Cite

This article investigates the impact of the p-p + junction (at the body-substrate interface) on different direct current (DC) and analog/radio frequency (RF) performance parameters of a newly invented structure called vertical superthin body field effect transistor (VSTB FET) through a well-calibrated TCAD tool. At a fixed body doping, the influence of p-p + junction was inspected for different substrate doping (N s ); which reveals that N s has a robust control on the device electrostatics. Interestingly, higher N s is seen to significantly suppress different short channel effects (SCEs), which in turn helps to improve various DC parameters excellently. An increase in N s from 10 15 to 10 18 cm À3 improves off-state leakage current and on-to-off current ratio by three orders of magnitude. Also, such a change in N s decreases subthreshold swing and drain-induced-barrier-lowering by 8.78 mV/dec and 11.15 mV/V, respectively. The underlying physics behind such improvement at higher N s is explored through the off-state channel electron density profiles corresponding to different N s values. Further, different analog/RF parameters such as transconductance, input capacitance, gate-drain capacitance, output conductance, gain-bandwidth-product, and transconductance frequency product (TFP) show slight improvement for increasing N s . In contrast, TGF, GFP, and GTFP offer large enhancement at higher N s . This study is expected to demonstrate the significance of N s on device performance.

show abstract

“…However, the shrinkage of FinFETs primarily demands high aspect ratio (height to width) of 3‐D thin fins that stand alone onto the substrate absolutely without any support. This requirement reduces the mechanical stability of fins in modern devices; also, the manufacturing process of such fins is becoming pretty challenging day by day as those can be broken or washed away anytime during the cleaning process by sonication method 7–13 . Therefore, such challenges associated with these novel devices encourage further evolution of device structure.…”

Section: Introductionmentioning

confidence: 99%

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

Self Cite

View full text Add to dashboard Cite

This article reports the DC and analog/radio frequency (RF) response of a newly invented device called vertical super‐thin body (VSTB) FET towards high‐k (Si3N4/HfO2) and low‐k (SiO2) gate dielectrics in conjunction with the scaling effect through a well‐calibrated Sentaurus TCAD tool. At channel length (LG) of 20 nm, compared to SiO2, Si3N4 improves various DC parameters such as off‐state leakage current (Ioff), on‐current (Ion), on‐to‐off current ratio (Ion/Ioff ratio), subthreshold swing (SS), and drain‐induced‐barrier‐lowering (DIBL) by 77.15%, 26.2%, one order of magnitude, 15.78%, and 36.2%, respectively. On the other hand, a higher improvement is seen in all these DC parameters for the HfO2 gate dielectric (Ioff, Ion, Ion/Ioff ratio, SS, DIBL improves respectively by 91.8%, 41.57%, two orders of magnitude, 28.28%, and 62.71%). The underlying physics behind such excellent improvement is explained by the device off‐state energy band diagram, electrostatic potential, and channel electron density profile for each dielectric. Further, for all the gate dielectrics considered, the device characteristics were studied for a wide range of LG from 10 to 50 nm to reveal the scaling impact on the device performance. Irrespective of the gate dielectric material, the device exhibits excellent performance at LG = 10 nm, which in turn indicates to the brilliant scalability of this new device. Besides, although Si3N4 and HfO2 increase gate capacitance (Cgg)/gate‐drain capacitance (Cgd), due to the extremely low values of Cgg/Cgd, enhanced unit gain cut‐off frequency, and gain‐bandwidth‐product is achieved. In addition, the increased transconductance (gm) of the device applying Si3N4/HfO2 gate dielectric leads to a higher peak value of TGF, intrinsic gain, TFP, GFP, and GTFP. This study intends to expand the fundamental knowledge about such a new device as a VSTB FET and hence, aims to be utilized in the future research of this novel device.

show abstract

An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

Cited by 17 publications

References 36 publications

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Contact Info

Product

Resources

About

An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

Cited by 17 publications

References 36 publications

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

The beneficial impact of a p–p + junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Contact Info

Product

Resources

About

The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET