Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling

Abstract

We demonstrate junctionless (JL) n-channel SOI nanowire FET with asymmetric spacer at nano regime. The impact of various spacer dielectrics on device performance is presented and various electrical characteristics are analyzed. The gate length (LG) scaling impact of the asymmetric spacer with various spacers on ION, IOFF, and ION/IOFF is analyzed. The device exhibits excellent electrical characteristics with SS = 64 mV/dec, DIBL = 45 mV/V, ION/IOFF = 106 even at 5 nm LG ensures better electrostatic integrity. From the result analysis it is noted that spacer plays a detrimental role in reducing OFF current (IOFF) at lower LG. Moreover, the power analysis on scaling with various spacer dielectrics is performed. The analog/RF performance is also performed and scaling feasibility with HfO2 spacer is presented. The result analysis ensures asymmetric JL nanowire FET is one of the possible options to continue scaling.