An industrial fault injection platform for soft-error dependability analysis and hardening of complex system-on-a-chip

Daveau, Jean-Marc; Blampey, Alexandre; Gasiot, Gilles; Bulone, J.; Roché, Philippe

doi:10.1109/irps.2009.5173253

Cited by 33 publications

(12 citation statements)

References 19 publications

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“…They are only available in existing hardware. accelerated hardware emulation These approaches [13,6] employe a detailed model of a target hardware, and simulate this model on an accelerator (usually a FPGA platform). The requirement of a detailed model usually means this is performed already at a later stage of a design workflow.…”

Section: Introductionmentioning

confidence: 99%

Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy

Carlson

Heirman

et al. 2012

Euro-Par 2011: Parallel Processing Workshops

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Abstract. As the capacity of caches increases dramatically with new processors, soft errors originating in cache memories has become a major reliability concern for high performance processors. This paper presents application specific soft error vulnerability analysis in order to understand an application's responses to soft errors from different levels of caches. Based on a high-performance processor simulator called Graphite, we have implemented a fault injection framework that can selectively inject bit flips to different levels of caches. We simulated a wide range of relevant bit error patterns and measured the applications' vulnerabilities to bit errors. Our experimental results have shown the differing vulnerabilities of applications to bit errors in different levels of caches (e.g. the application failure rate for one program is more than the doulbe of that for another program for a given cache); the results have also indicated the probabilities of different failure behaviors for the given applications.

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Section: Introductionmentioning

confidence: 99%

Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy

Carlson

Heirman

et al. 2012

Euro-Par 2011: Parallel Processing Workshops

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“…However, these campaigns represent only a fragment of all possible SEU failures, and computed values lack of confidence margins. Statistical Fault Injection (SFI) proposes to randomly select a reduced number of the possible erroneous configurations and, by statistical analysis, gives robustness measures and confidence margins on the results [9,23].…”

Section: Introductionmentioning

confidence: 99%

Feasibility analysis for robustness quantification by symbolic model checking

Baarir

Braunstein

Encrenaz

et al. 2011

Form Methods Syst Des

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We propose and investigate a robustness evaluation procedure for sequential circuits subject to particle strikes inducing bit-flips in memory elements. We define a general fault model, a parametric reparation model and quantitative measures reflecting the robustness capability of the circuit with respect to these fault and reparation models. We provide algorithms to compute these metrics and show how they can be interpreted in order to better understand the robustness capability of several circuits (a simple circuit coming from the VIS distribution, circuits from the itc-99 benchmarks and a CAN-Bus interface).

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“…More recently, the partialreconfiguration features of FPGAs for fault injection [2], [21] and large parallel emulators al. [8] have been utilized. Ongil et al [20] discuss various types of fault injection techniques for medium-size non-programmable circuits.…”

mentioning

confidence: 99%

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors

Sauer

Tomashevich

Müller

et al. 2011

2011 IEEE 17th International on-Line Testing Symposium

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Abstract-State-of-the-art cyber-physical systems are increasingly deployed in harsh environments with non-negligible soft error rates, such as aviation or search-and-rescue missions. State-of-the-art nanoscale manufacturing technologies are more vulnerable to soft errors. In this paper, we present an FPGAbased framework for injecting soft errors into user-specified memory elements of an entire microprocessor (MIPS32) running application software. While the framework is applicable to arbitrary software, we demonstrate its usage by characterizing soft errors effects on several software filters used in aviation for probabilistic sensor data fusion.

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An industrial fault injection platform for soft-error dependability analysis and hardening of complex system-on-a-chip

Cited by 33 publications

References 19 publications

Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy

Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy

Feasibility analysis for robustness quantification by symbolic model checking

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors

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