An improved path enumeration method considering different fall and rise gate delays

Güntzel, José Luís; Pinto, Ana Cristina Medina; Moraes, Fernando; Reis, Ricardo

doi:10.1109/sbcci.1998.715443

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…The adopted path tracing procedure is an extension of the Best-First Search procedure proposed by Yen et al [11], modified to consider separate fall and rise gate delays [12]. This procedure begins by creating a circuit graph (DAG) and computing the "maximum delay to terminal" (mdt) to each graph node, beginning by nodes that represent the primary outputs.…”

Section: Path Tracingmentioning

confidence: 99%

Finding the critical delay of combinational blocks by floating vector simulation and path tracing

Wilke¹,

Guntzel²,

Bystronski³

et al.

Proceedings. 15th Symposium on Integrated Circuits and Systems Design

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The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. Electric-level simulation is more accurate but may not be applied to large combinational blocks due to the long execution time to simulate all possible input situations. A possible solution would be simulating only the input patterns responsible for the critical operation. However there is no method that guarantees finding such input patterns. The other solution, timing analysis, does not present the same accuracy as simulation, mainly when the analyzer does not take false paths into account. On the other hand, false path-aware timing analyzers either are too time consuming or are not able to furnish information on the long false paths.In this paper we propose a timing verification tool based on floating vector simulation and path tracing able to identify the "true" critical delay of combinational blocks. It is also able to identify the long false paths that a combinational block may contain. Although being limited by the number of inputs of the combinational block to be analyzed, it also furnishes some valuable information on the circuit under analysis that may help the designer to take some important decisions and also to understand the impact of the chosen technology mapping parameters on the timing behavior of the circuit.

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Section: Path Tracingmentioning

confidence: 99%

Finding the critical delay of combinational blocks by floating vector simulation and path tracing

Wilke¹,

Guntzel²,

Bystronski³

et al.

Proceedings. 15th Symposium on Integrated Circuits and Systems Design

Self Cite

View full text Add to dashboard Cite

show abstract

“…The used path tracing procedure is an extension of the Best-First Search procedure proposed by Yen et al [11], modified to consider separate fall and rise gate delays [12]. This procedure begins by creating a circuit graph (DAG) and computing the "maximum delay to terminal" (mdt) to each graph node, beginning by nodes that represent the primary outputs.…”

Section: Path Tracingmentioning

confidence: 99%

Improving critical path identification in functional timing analysis

Ferrao¹,

Wilke²,

Reis³

et al.

16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.

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†True critical path identification is still an issue of relevant importance in the physical design of CMOS VLSI circuits. Although delay enumeration-based timing analysis methods are independent of the number of long false paths, they are not able to identify the true critical paths of a combinational block. Hence, path enumeration-based timing analysis must be used.In this paper we present a new heuristic for ordering the objectives that need to be satisfied for declaring a path as sensitizable. The new heuristic is compared to the commonly used one, which relies on following the logical depth of the circuit. The practical results showed that the proposed heuristic tends to provide better results.

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