Finding the critical delay of combinational blocks by floating vector simulation and path tracing

Abstract

The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. Electric-level simulation is more accurate but may not be applied to large combinational blocks due to the long execution time to simulate all possible input situations. A possible solution would be simulating only the input patterns responsible for the critical operation. However there is no method that guarantees finding such input patterns. The other solution, timing analysis, does not present the same accuracy as simulation, mainly when the analyzer does not take false paths into account. On the other hand, false path-aware timing analyzers either are too time consuming or are not able to furnish information on the long false paths.In this paper we propose a timing verification tool based on floating vector simulation and path tracing able to identify the "true" critical delay of combinational blocks. It is also able to identify the long false paths that a combinational block may contain. Although being limited by the number of inputs of the combinational block to be analyzed, it also furnishes some valuable information on the circuit under analysis that may help the designer to take some important decisions and also to understand the impact of the chosen technology mapping parameters on the timing behavior of the circuit.

A visual simulation tool at layout level

“…In order to provide not only a purely logic simulation of the circuit, it is important to take into account the information referring to the timing of circuits that will be simulated [4]. A timing analysis tool under development at our group will have un interface with the visual simulation tool, So, it will be possible to have the option of a visual output of the timing analyses results.…”