An improved architecture to generate sinusoidal signal using diect digital frequency synthesis technique

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

“…The required data can be read by selecting the word-line and digit line. So through the planning of ROM, half-size ROM is needed [12]. Figure 14 is the complete structure of the circuit which can distinguish quadrant, invoke ROM, and combine ROM and output with two ROMs as the center.…”