An implementation and analysis of a concurrent built-in self-test technique

Sharma, Rupendra Kumar; Saluja, Kewal K.

doi:10.1109/ftcs.1988.5315

Cited by 36 publications

(18 citation statements)

References 3 publications

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“…Nevertheless, all input combinations still need to appear before any indication of circuit correctness is provided. In [4], a test vector based self-test method is described and evaluated for combinational circuits.…”

Section: Related Workmentioning

confidence: 99%

Non-intrusive design of concurrently self-testable FSMs

Drineas

Makris

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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We propose a methodology for non-intrusive design of concurrently self-testable FSMs. The proposed method is similar to duplication, wherein a replica of the original FSM acts as a predictor that immediately detects potential faults by comparison to the original FSM. However, instead of duplicating the complete FSM, the proposed method replicates only a minimal portion adequate to detect all possible faults, yet at the cost of introducing potential fault detection latency. Furthermore, in contrast to concurrent error detection approaches, which presume the ability to resynthesize the FSM and exploit parity-based state encoding, the proposed method is non-intrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results on FSMs of various sizes and densities indicate that the proposed method detects 100% of the faults with very low average fault detection latency. Furthermore, a hardware overhead reduction of up to 33% is achieved, as compared to duplication-based concurrent error detection.

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Section: Related Workmentioning

confidence: 99%

Non-intrusive design of concurrently self-testable FSMs

Drineas

Makris

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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“…The second fault may invalidate the reference values used for testing the circuit. In addition, in schemes that rely on specific test vectors [4], the presence of one fault may invalidate a test for another fault [1].…”

Section: Introductionmentioning

confidence: 98%

“…For example, in [3], output comparison of identical circuits under identical input vectors is used. In [4], a circuit named CTC , which produces the same output values as the CUT for a given set of test vectors T , is implemented. The input vectors applied to the CUT are also applied to CTC .…”

Section: Introductionmentioning

confidence: 99%

Reducing fault latency in concurrent on-line testing by using checking functions over internal lines

Pomeranz

Reddy

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

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We describe a method to reduce the fault latency, i.e., the time it takes to detect a fault after it occurs, during concurrent on-line testing. A high fault latency can negatively affect the fault coverage in various ways. The fault latency is reduced by using what we call checking functions. A checking function cf i expresses the function of a line g i in the circuit as a function of one or more other lines. During concurrent on-line testing, the value of g i is compared to the value of cf i . A mismatch indicates the presence of a fault. The advantage of checking functions is that they only use lines that already exist in the circuit. We demonstrate that benchmark circuits have large numbers of checking functions to choose from. We also demonstrate the increase in fault coverage and the reductions in fault detection times possible by using checking functions.

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“…Finally, a concurrent fault detection method for combinational logic is described in [11]. This method, which we will refer to as Test Vector Logic Replication (TVLR), is depicted in Figure (1).…”

Section: Related Workmentioning

confidence: 99%

“…Similarly to [2,3,11], we assume a uniform distribution at the circuit inputs and employ fault simulation of randomly generated input sequences. More specifically, for each method we use HOPE [15] to perform two fault simulations of the same sequence of randomly generated inputs, once observing both the test output and the circuit outputs, and a second time observing only the test output.…”

Section: Fault Detection Latencymentioning

confidence: 99%