Concurrent fault detection in random combinational logic

Drineas, Petros; Makris, Yiorgos

doi:10.1109/isqed.2003.1194770

Cited by 25 publications

(8 citation statements)

References 11 publications

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“…Concurrent on-line built-in self-test techniques such as Built-In Concurrent Self-Test (BICST) [6] and Reduced Observation Width Replication (ROWR) [7] provide high fault coverage at low area overhead but only consider a limited subset of pre-computed test vectors. Hence these approaches are likely to miss faults occurring in a normal circuit operation.…”

Section: Related Workmentioning

confidence: 99%

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Saltarelli

Niazmand

Raik

et al. 2015

2015 Euromicro Conference on Digital System Design

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This paper proposes a framework for automated evaluation of concurrent online checkers. The novelty of the underlying approach lies in its completeness (i.e. ability of formally proving the presence or absence of true misses), minimal fault detection latency and accurate, fully automated evaluation of the fault detection characteristics of the checkers. The methodology consists of creating a pseudo-combinational version of the circuit under test, specifying the environment in terms of valid input stimuli and providing the assertions for generating the checkers, which will thereafter be evaluated by the framework. In this paper, a case-study on the control part (routing and arbitration) of a Network-on-Chip (NoC) router has been carried out. It shows on a realistic application that the framework is capable of accurately and formally evaluating the quality of individual concurrent checkers which constitutes an important task in fault tolerant system design. The case study shows that the proposed approach helps achieving high fault coverage in a single clock-cycle.

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Section: Related Workmentioning

confidence: 99%

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Saltarelli

Niazmand

Raik

et al. 2015

2015 Euromicro Conference on Digital System Design

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show abstract

“…The error monitoring circuit could be based on a number of runtime error detection approaches (e.g. logic implications [35]- [37], parity check codes [38], [39] selective duplication [40], etc). Table II. For this example, we assume that the error monitoring circuit is in place in the original ASIC layer and is able to trigger the dynamic reconfiguration of the FPGA layer for proper repair.…”

Section: Architecture and Multiplier Repairmentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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3D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an FPGA that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a non-programmable die by replacing the defective functionality with functionality on the FPGA. In this article, we discuss what additional logic must be added to an ASIC die to allow such a bypass to occur. We then show through detailed simulation of a 2.5D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies.Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

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“…While effective, these techniques generally incur a large area overhead. To reduce the footprint of the detection/protection circuitry, a number of approaches focus on protecting only a portion of the system considered critical [Samudrala et al 2004;Webb and Liptay 1997], while other techniques, such as the Built-In Concurrent Self Test (BICST) [Sharma and Saluja 1988] and the Reduced Observation Width Replication (ROWR) [Drineas and Makris 2003] limit overhead by focusing on a portion of the available input space.…”

Section: Related Workmentioning

confidence: 99%

Using implications to choose tests through suspect fault identification

Dworak

Nepal

Alves

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this article, we will investigate the diagnostic capability of logic implications to identify possible failure locations when an error is detected online. We will then utilize this information to select a highly efficient test set that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system.

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Concurrent fault detection in random combinational logic

Abstract: We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic.

Cited by 25 publications

References 11 publications

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Repairing a 3-D Die-Stack Using Available Programmable Logic

Using implications to choose tests through suspect fault identification

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