Using implications to choose tests through suspect fault identification

Abstract

As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this article, we will investigate the diagnostic capability of logic implications to identify possible failure locations when an error is detected online. We will then utilize this information to select a highly efficient test set that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system.

Repairing a 3-D Die-Stack Using Available Programmable Logic

“…The error monitoring circuit could be based on a number of runtime error detection approaches (e.g. logic implications [35]- [37], parity check codes [38], [39] selective duplication [40], etc). Table II. For this example, we assume that the error monitoring circuit is in place in the original ASIC layer and is able to trigger the dynamic reconfiguration of the FPGA layer for proper repair.…”

“…While, the exact nature of the diagnosis approach in a 3D IC stack is outside the scope of this article and a subject of our future investigations, our previous work [35]- [37] on online error detection in a 2D IC could be adapted to identify the location of some defective behavior in a 3D stack. For example, we have previously demonstrated that when logic implications are used for online-error detection, determining which implication was violated provides automatic diagnostic data because each implication can only protect a well-defined subset of all possible circuit sites [37].…”

“…For example, we have previously demonstrated that when logic implications are used for online-error detection, determining which implication was violated provides automatic diagnostic data because each implication can only protect a well-defined subset of all possible circuit sites [37]. If all the suspected circuit sites are located within a single partition, the exact partition to be repaired can be identified automatically.…”

Test compaction techniques for assertion-based test generation

“…Another approach uses logic implications [Dworak et al 2012] and well-established implication-based techniques [Bushnell and Agrawal 2000]. In this method, logic implications define the expected relationships between values at different circuit sites.…”