An IEEE 802.11a/b/g SoC for Embedded WLAN Applications

Nathawad, L.Y.; Weber, D.; Abdollahi, Shahram; Chen, P.; Enam, S.K.; Kaczynski, B.; Kheirkhahi, A.; Lee, MeeLan; Limotyrakis, S.; Onodera, K.; Vleugels, K.; Zargari, M.; Wooley, B.A.

doi:10.1109/isscc.2006.1696193

Cited by 23 publications

(6 citation statements)

References 4 publications

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“…However, since our traces were collected from 54Mbps interfaces, the MAT-LAB simulator still uses 54Mbps. Moreover, the state-of-the-art implementations, including MAX2829 used in our experiments in Section 6 [13], have power-saving modes with more percentage power reduction with smaller overhead [22] [14]. Therefore, we expect µPM will perform even better with modern 802.11 interfaces than what reported below.…”

Section: Two Complementary Simulatorsmentioning

confidence: 95%

“…For example, the PRISM 802.11 transceiver provides four power-saving modes with power reduction from 34% to 90%, with latency from 1us to 5ms, respectively [1]. More importantly, the rapid development in RF circuit design has resulted in power-saving modes of lower power and shorter wake-up latency, as apparent from the 802.11 transceiver and frequency synthesizer design reported in recent years [22] [14]. Due to the energy overhead of mode transition, there is a minimum length of idle interval to justify the use of a power-saving mode.…”

Section: Power-saving Modesmentioning

confidence: 99%

“…Our measurement shows that 802.11 interfaces on laptops can easily spend over 80% of its busy time and energy in waiting for frames through idle intervals below 200ms. Meanwhile, advancement in RF IC design has made it profitable for a wireless interface to enter a powersaving mode for as short as several microseconds (µs), because the time and energy costs of using power-saving modes have been dramatically reduced in recent years [1] [22] [14].…”

Section: Introductionmentioning

confidence: 99%

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Micro power management of active 802.11 interfaces

Liu

Lin

2008

Proceedings of the 6th International Conference on Mobile Systems, Applications, and Services

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Wireless interfaces are major power consumers on mobile systems. Considerable research has improved the energy efficiency of elongated idle periods or created more elongated idle periods in wireless interfaces, often requiring cooperation from applications or the network infrastructure. With increasing wireless mobile data, it has become critical to improve the energy efficiency of active wireless interfaces. In this work, we present micro power management (µPM), a solution inspired by the mismatch between the high performance of state-of-the-art 802.11 interfaces and the modest data rate requirements by many popular network applications. µPM enables an 802.11 interface to enter unreachable power-saving modes even between MAC frames, without noticeable impact on the traffic flow. To control data loss, µPM leverages the retransmission mechanism in 802.11 and controls frame delay to adapt to demanded network throughput with minimal cooperation from the access point. Based on a theoretical framework, we employ simulation to systematically investigate an effective and efficient implementation of µPM. We have built a prototype µPM on an openaccess wireless hardware platform. Measurements show that more than 30% power reduction for the wireless transceiver can be achieved with µPM for various applications without perceptible quality degradation.

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Section: Two Complementary Simulatorsmentioning

confidence: 95%

Section: Power-saving Modesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Micro power management of active 802.11 interfaces

Liu

Lin

2008

Proceedings of the 6th International Conference on Mobile Systems, Applications, and Services

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“…2 [7,8,9,10,11,12,13,14,15,16]. Please note that WLAN employs multiple-input multiple-output (MIMO) technology [13], and multiple transceivers are implemented in one chip.…”

Section: Trends Of Rf Transceiver Performancementioning

confidence: 99%

Recent progress in CMOS RF circuit design

Kousai

2014

IEICE Electron. Express

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This paper reviews recent progress in CMOS RF circuits with respect to technology scaling. It tunes out that RF transceivers almost ideally scale with technologies, even though some of RF circuits do not obey scaling law due to the noise, linearity, matching, and output power constraints. In order to overcome these constraints many design techniques including all digital approach, digital assisted approach, noise cancelling, non-linearity canceling, and RF filtering have been introduced. Also remaining challenges for the future is discussed.

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“…Although WLAN system-on-chip (SoC) solutions [3] have been successfully developed in a complementary metaloxide semiconductor (CMOS) to address this demand, the silicon area (45 mm 2 ) and power dissipation (400 mW) are currently still sizable for many embedded systems. Dominated by the digital logic and memory that perform various system-level functions in the physical layer, WLAN SoCs are indeed capable of taking advantage of nanoscale technologies for cost and power reduction [4].…”

Section: Introductionmentioning

confidence: 99%

Experimental 1-V flexible-IF CMOS analogue-baseband chain for IEEE 802.11a/b/g WLAN receivers

Mak

Martins

2007

IET Circuits Devices Syst.

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A low-voltage low-power analogue-baseband chain designed for IEEE 802.11a/b/g wireless local-area network (WLAN) receivers is described. It features architecturally a 'two-step channel selection' to complement the radio front-end, and a flexible intermediate frequency (IF) reception capability to alleviate the cancellation of frequency and DC-offset. In circuit implementation, a double-quadrature downconverter based on a 'series-switching' mixerquad realises a wideband-accurate I/Q demodulation. A 'switched-current-resistor' programmable-gain amplifier (PGA) minimises the bandwidth variation and transient in gain tuning by stabilising, concurrently, the PGA's feedback factor and quiescent-operating point. An 'inside-OpAmp' DC-offset canceller creates area-efficiently a very low cutoff frequency high-pass pole at DC while providing a fast settling of DC-offset transients. Fabricated in a 0.35 mm complementary metal-oxide semiconductor (CMOS) process without resorting to any specialised device, the prototype consumes 14 mW per channel at 1 V. The transient time in a 52-dB gain step is ,1 ms and the stopband rejection ratio at 20/40 MHz is 32/90 dB. The error vector magnitudes are 227 and 217 dB for 802.11a/g and b modes, respectively.

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An IEEE 802.11a/b/g SoC for Embedded WLAN Applications

Cited by 23 publications

References 4 publications

Micro power management of active 802.11 interfaces

Micro power management of active 802.11 interfaces

Recent progress in CMOS RF circuit design

Experimental 1-V flexible-IF CMOS analogue-baseband chain for IEEE 802.11a/b/g WLAN receivers

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