Experimental 1-V flexible-IF CMOS analogue-baseband chain for IEEE 802.11a/b/g WLAN receivers

Abstract

A low-voltage low-power analogue-baseband chain designed for IEEE 802.11a/b/g wireless local-area network (WLAN) receivers is described. It features architecturally a 'two-step channel selection' to complement the radio front-end, and a flexible intermediate frequency (IF) reception capability to alleviate the cancellation of frequency and DC-offset. In circuit implementation, a double-quadrature downconverter based on a 'series-switching' mixerquad realises a wideband-accurate I/Q demodulation. A 'switched-current-resistor' programmable-gain amplifier (PGA) minimises the bandwidth variation and transient in gain tuning by stabilising, concurrently, the PGA's feedback factor and quiescent-operating point. An 'inside-OpAmp' DC-offset canceller creates area-efficiently a very low cutoff frequency high-pass pole at DC while providing a fast settling of DC-offset transients. Fabricated in a 0.35 mm complementary metal-oxide semiconductor (CMOS) process without resorting to any specialised device, the prototype consumes 14 mW per channel at 1 V. The transient time in a 52-dB gain step is ,1 ms and the stopband rejection ratio at 20/40 MHz is 32/90 dB. The error vector magnitudes are 227 and 217 dB for 802.11a/g and b modes, respectively.

Design of Baseband Analog Chain with Optimum Allocation of Gain and Filter Rejection for WLAN Applications

“…An SFDR of 63.9 dB is achieved. The measurement results are compared with those of previously reported analog baseband chains [13][14][15] in Table 3. In the proposed receiver baseband analog chain, the overall SFDR is maximized with the optimum allocation of the gain and filter rejection using the proposed design methodology.…”