An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

Ullah, Anees; Sánchez, Ernesto; Sterpone, Luca; Cardona, Luis Andres; Ferrer, Carles

doi:10.1016/j.microrel.2017.06.032

Cited by 15 publications

(2 citation statements)

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“…Compared to accelerated beam tests carried out in radiation facilities [4] or physical reliability tests perfomed in rooms at cryogenic temperatures, fault emulation approaches provide great versatility to test different designs in a short amount of time while simultaneously keeping costs low. Besides that, fault emulation can reduce timing requirements and provides more realistic results than simulation-based set-ups, which can be used to perform an accurate analysis of the design's behavior [5]. These designs may be deployed in field-programmable gate array (FPGA) or application-specific integrated circuits (ASICs), hence the error model differs and the platform's hardware has to be carefully selected.…”

Section: Introductionmentioning

confidence: 99%

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

et al. 2021

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There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory represents the majority of the memory elements in an FPGA. However, an FPGA-based platform could also be exploited to support the emulation of transient and permanent errors for designs intended to work in application-specific integrated circuits (ASICs) or radiation-hardened devices such as antifuse FPGAs. In this context, the obtention of a particular set of bits to flip is required to be able to emulate these error models. The main difficulty of this approach lies in determining the mentioned set of bits, which is due to the unavailability of a public description of the bitstream and the lack of FPGA architecture details. To help with this issue, we present a methodology to determine specific configuration memory bits from SRAM-based FPGAs that, when flipped, emulate permanent or transient upsets in any flip-flop element of the design under test. This methodology is proved in recent FPGA technologies and provides great control and precision in reliability experiments for harsh environments.

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Section: Introductionmentioning

confidence: 99%