Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

Abstract

There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory represents the majority of the memory elements in an FPGA. However, an FPGA-based platform could also be exploited to support the emulation of transient and permanent errors for designs intended to work in application-specific integrated circuits (ASICs) or radiation-hardened devices such as antifuse FPGAs. In this context, the obtention of a particular set of bits to flip is required to be able to emulate these error models. The main difficulty of this approach lies in determining the mentioned set of bits, which is due to the unavailability of a public description of the bitstream and the lack of FPGA architecture details. To help with this issue, we present a methodology to determine specific configuration memory bits from SRAM-based FPGAs that, when flipped, emulate permanent or transient upsets in any flip-flop element of the design under test. This methodology is proved in recent FPGA technologies and provides great control and precision in reliability experiments for harsh environments.

Fault Detection and Analysis in SRAM through Self Refreshing Operation

“…The operational voltages have been reduced further in order to meet the minimal power allowance. Due to ray attacks, the durability of the IC is impaired in use in space due to both the decrease in dimension and voltage scalability [1][2]. The voltage changes and potential for mistakes that result from ray hits on semiconductor substances are caused by charged particles.…”