An experimental 35ns 1Mb biCMOS DRAM

Abstract

AN EXPERIMENTAL I Rlb bipolar CMOS (Hi-BiCMOS) DRAMwith a typical access time of 35ns and typical power dissipation of 450mW at a 60ns cycle time, will be reported.The key to achieving high-speed DRAMs is to introduce high performance bipolar transistors, while maintaining high soft-error immunity, low-power dissipation and low-peak current, even at cycle times shorter than 100ns. Four developments are proposed to meet these requirements: a Hi-BiCMOS DRAM device structure', a high-speed bipolar circuitry combined with a highspeed memory array configuration, a BiCMOS clock driver suitable for an owchip voltage limiter and a current mirror circuit combined with a voltage limiter.