A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

Lu, Nicky; Hua, Changzhou; Hwang, Wei; Henkels, W.H.; Rajeevakumar, T.V.; Hanafi, H.I.; Terman, Lewis M.; Franch, R.

doi:10.1109/4.5936

IEEE J. Solid-State Circuits

1988

DOI: 10.1109/4.5936

|View full text |Cite

A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

Nicky Lu

Changzhou Hua

Wei Hwang

et al.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

1989

1995

Publication Types

Select...

Article6

Relationship

Self Cite0

Independent6

Authors

Journals

Cited by 19 publications

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The chip Some circuit design techniques explored in previous highhas a total of 16 such 128Kb subarrays. Two I/O pads are placed speed DRAMs are also used[6][7][8], Fast RAS access times close to their array blocks.peripheral areas. In addition to the address receivers, the bottom peripheral area contains all control signal input circuits for RAS, CAS, WE, and OE.…”

mentioning

confidence: 99%

A 64Kb × 32 DRAM for graphics applications

Sunaga¹,

Hosokawa²,

Dhong

et al. 1995

IBM J. Res. & Dev.

View full text Add to dashboard Cite

A high-speed 2Mb CMOS DRAM with 32 data l/Os is described. A 0.6-yum CMOS process with a single poiysiiicon layer, two levels of metal, and substrate-plate trench-capacitor (SPT) memory cells is used to fabricate the chip. It is designed to provide the wide data bandwidth required by high-performance graphics applications. A 35-ns access time with an 80-ns cycle time has been demonstrated. The 32-bit data bus and the high-speed feature achieve more than two times better graphics performance than conventional dual-port memories. A sensing method with a 2/3 V^^ bit-line precharge voltage and a limited bit-line voltage swing is exploited to optimize speed and power. The chip, which operates on a 5-V power supply, dissipates 140 mA at the 80-ns cycle time.

show abstract

mentioning

confidence: 99%

A 64Kb × 32 DRAM for graphics applications

Sunaga¹,

Hosokawa²,

Dhong

et al. 1995

IBM J. Res. & Dev.

View full text Add to dashboard Cite

show abstract

Electron beam testing of circuits at liquid nitrogen temperature

1990

View full text Add to dashboard Cite

show abstract

Trends in semiconductor memories

Maes

Groeseneken

Lebon

et al. 1989

Microelectronics Journal

View full text Add to dashboard Cite

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

hi@scite.ai

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

Cited by 19 publications

References 7 publications

A 64Kb × 32 DRAM for graphics applications

A 64Kb × 32 DRAM for graphics applications

Electron beam testing of circuits at liquid nitrogen temperature

Trends in semiconductor memories

Contact Info

Product

Resources

About