An experimental 1.5-V 64-Mb DRAM

Nakagome, Y.; Tanaka, Hiroki; Takeuchi, Kazuhiro; Kume, E.; Watanabe, Yoshio; Kaga, T.; Kawamoto, Y.; Murai, F.; Izawa, R.; Hisamoto, D.; Kisu, T.; Nishida, Takashi; Takeda, Eiji; Itoh, K.

doi:10.1109/4.75040

Cited by 167 publications

(54 citation statements)

References 8 publications

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“…This would avoid large V DROP . However, Nakagome et al (1991) CrossLoad CP suffers from low conduction due to gate drive capabilities of PMOS load switches and no gains from series switches when V IN <V TH or when V OUT is minute due to heavy loads (Kim et al, 2015). Recently, literatures in (Favrat et al, 1998;Chen et al, 2010;Ulaganathan et al, 2012;Kim et al, 2015) provide improved versions of this Cross-Load CP (Nakagome et al, 1991) to enhance these constraints associated to LV start-up operations.…”

Section: Cross-coupled Charge Pumpmentioning

confidence: 99%

“…5b. These dual-branch structures were introduced to lower ripples in the CTS design (Kleveland, 2002;New et al, 2012) and later evolved into latch-based designs (Nakagome et al, 1991;Gariboldi and Pulvirenti, 1994;1996;Favrat et al, 1998;Pelliconi et al, 2003;Ker et al, 2006;Che et al, 2009;Chen et al, 2010;Ulaganathan et al, 2012;Peng et al, 2014;Kim et al, 2015) which are currently gaining popularity. These structures have V OUT similar to Equation 1 but with reduced charge transfer intervals of T/2 (Palumbo and Pappalardo, 2010), circuit minimization with smaller C PUMP values and half the ripple, V R compared to single branch CPs where V R is expressed as V R = I OUT T/[2(C OUT +C PUMP )] (Pan and Samaddar, 2010) assuming C OUT >> C PUMP .…”

Section: Dual-branch Charge Pumpmentioning

confidence: 99%

“…Moreover, such body-biasing will cause leakages if not well controlled. An alternative was Nakagome et al (1991) circuit (Fig. 7a) which utilizes cross-coupled NMOS cells to obtain lifted voltage levels where differential outputs of the cells are coupled to form a single output using dual series-connected PMOS load switches (Nakagome et al, 1991).…”

Section: Cross-coupled Charge Pumpmentioning

confidence: 99%

“…7. Cross-couple charge pumps with various body biasing topologies (a) cross-loads (Nakagome et al, 1991) (b) bulk-switching (Favrat et al, 1998) (c) forward body-biasing (Chen et al, 2010) (d) dynamic body-biasing (Kim et al, 2015) To resolve lower conduction levels of the Cross-Load CP (Nakagome et al, 1991;Favrat et al, 1998) proposed a Bulk-Switching CP (Fig. 7b) with better switch conductance due to a level shifter gate signal control but this Bulk-Switching fails at low voltages due to backward current via series switches (Kim et al, 2015).…”

Section: Cross-coupled Charge Pumpmentioning

confidence: 99%

See 3 more Smart Citations

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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This paper reviews CMOS based charge pump topologies used within autonomous embedded micro-systems. These charge pump structures have evolved from its simplistic diode-tied, single-branches with major threshold drops to exponential type, dual-branches with sophisticated gate and substrate control for lower voltage operation. Published charge pumps are grouped based on architecture, operation principles and pump optimization techniques with their pros and cons compared and results contrasted. The various charge pump topologies and schemes used are considered based on pumping efficiency, power efficiency, charge transferability, circuit complexity, pumping capacitors, form factor and minimum supply voltages with an optimum load. This article concludes with an overview of suitable techniques and recommendations that will aid a designer in selecting the most suitable charge pump topology especially for low ambient micro energy harvesting applications.

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Section: Cross-coupled Charge Pumpmentioning

confidence: 99%

Section: Dual-branch Charge Pumpmentioning

confidence: 99%

Section: Cross-coupled Charge Pumpmentioning

confidence: 99%

Section: Cross-coupled Charge Pumpmentioning

confidence: 99%

See 2 more Smart Citations

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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show abstract

“…In Figure 6.14 the capacitor (now C2) is precharged through an nMOS switch M2. The capacitor can be charged to V DD since the gate of M2 is controlled by a boosted voltage generated with M1 and C1 [132]. The well bias for the pMOS transistor M3 is produced with another charge pump.…”

Section: Gate Voltage Boostingmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Linear distribution of capacitance in Dickson charge pumps to reduce rise time

Ballo

Grasso

Palumbo

et al. 2020

Circuit Theory & Apps

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Summary This paper introduces a design strategy to reduce rise time of charge pumps maintaining equal the silicon area, which is effective when the load capacitance is lower than the total charge pump capacitance. The strategy relies on an unconventional pumping capacitors sizing, which set them not equal and follows a linear distribution. The approach is based on a theoretical analysis and is validated through post‐layout simulations using a 130‐nm complementary metal‐oxide semiconductor (CMOS) standard technology. The simulations demonstrate the advantages of the proposed design strategy and the accuracy of the theory.

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An experimental 1.5-V 64-Mb DRAM

Cited by 167 publications

References 8 publications

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Linear distribution of capacitance in Dickson charge pumps to reduce rise time

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