An evaluation of the TRIPS computer system

Abstract

The TRIPS system employs a new instruction set architecture (ISA) called Explicit Data Graph Execution (EDGE) that renegotiates the boundary between hardware and software to expose and exploit concurrency. EDGE ISAs use a block-atomic execution model in which blocks are composed of dataflow instructions. The goal of the TRIPS design is to mine concurrency for high performance while tolerating emerging technology scaling challenges, such as increasing wire delays and power consumption. This paper evaluates how well TRIPS meets this goal through a detailed ISA and performance analysis. We compare performance, using cycles counts, to commercial processors. On SPEC CPU2000, the Intel Core 2 outperforms compiled TRIPS code in most cases, although TRIPS matches a Pentium 4. On simple benchmarks, compiled TRIPS code outperforms the Core 2 by 10% and hand-optimized TRIPS code outperforms it by factor of 3. Compared to conventional ISAs, the block-atomic model provides a larger instruction window, increases concurrency at a cost of more instructions executed, and replaces register and memory accesses with more efficient direct instruction-to-instruction communication. Our analysis suggests ISA, microarchitecture, and compiler enhancements for addressing weaknesses in TRIPS and indicates that EDGE architectures have the potential to exploit greater concurrency in future technologies.

An Instruction Mapping Scheme for FU Array Accelerator

“…The shortage of LD/ST units will usually be the bottleneck for the whole system. TRIPS [8] supports the Explicit Data Graph Execution (EDGE) [15] instruction set architecture (ISA), in which instructions are designed to explicitly indicate the operations and the connections between these operations. As demonstrated from their results, TRIPS highly depends on the efficiency of the compiler to generate perfect dataflow controls.…”

“…However, in contrast to its good energy efficiency, CGRAs usually lack programmability, and thus require a special compiler [5], [6] to generate configuration information. This is similar to logic synthesis tools and a special ISA [7], [8], which explicitly specifies data flows between FUs.…”

M5 based EDGE architecture modeling

“…Although Wavescalar [3], TRIPS [4] and TFlex [5] have been invented and published over the past decade, all of them use privately developed simulation tools. The TRIPS group at UT-Austin developed a suite of simulation tools for TRIPS and TFlex called tsim [ 12], which is available by request, but which is not built on any well-known infrastructure and designed at a low level for a specific architecture.…”

“…Finally, instruction blocks are committed atomically, in program order, to update the machine state. We do not discuss more detailed features of general EDGE architectures since they have been previously pub lished [14][1] [4].…”

“…Although researchers have been exploring EDGE archi tectures for nearly ten years since 2001, with some innova tive resulting micro architectures [3] [ 4][S], there is still no support for EDGE architectures in common open source simulators such as SimpleScalar, SimOS, SIMICS, and MS. Research groups focusing on EDGE architectures usually use simulators developed privately with limited open source features. More importantly, these simulators are specific to concrete implementations, which narrows the published research achievements to implementation-centric area and makes it difficult to research new designs.…”