An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS

Wooters, Stuart N.; Calhoun, Benton H.; Blalock, Travis N.

doi:10.1109/tcsii.2010.2043471

Cited by 106 publications

(66 citation statements)

References 11 publications

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“…This is because of the quadratic dependence of the power dissipation on the supply voltage [2]. The delay variation occurs due to different current driving capabilities of transistors [8] [9]. The level shifters are required to function appropriately when the difference between the two voltage levels is high.…”

Section: Introductionmentioning

confidence: 99%

“…It is considered as the main disadvantage of this architecture which is also responsible for greater static power dissipation. The Wooterset al reported LS topology a single supply level shifter for low power and high speed applications composed of two stages [8]. The first stage is the conventional DCVS circuit which is used to generate rail to rail swing.…”

Section: Introductionmentioning

confidence: 99%

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Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

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Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

View full text Add to dashboard Cite

show abstract

“…It is widely used in multi-rail power supply on-chip systems, such as Very Large Scale Integration circuit (VLSI), Micro-Electro-Mechanical Systems (MEMS), mixed-signal integrated circuits and power-conversion systems [1][2][3][4][5][6][7][9][10][11][14][15][16][17][18][20][21][22][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

“…For low voltage applications [3,10,20,25,26], with the supply voltage of logic circuit decreasing to subthreshold while the supply voltage of analog circuit remains unchanged, level shifter comes across new challenges [3]. The conventional level shifter design based on differential cascode voltage switch topology is limited for robust up-conversion from sub-threshold to super-threshold.…”

Section: Introductionmentioning

confidence: 99%

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

Lai

Zhong

et al. 2017

Circuits Syst Signal Process

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In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module "inverse Schmitt trigger" to drive the pull-up transistors of conventional HVLS. As a result, the "Miller Plateau" caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5μm high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.

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“…However, generation of intermediate voltages requires voltage regulators that incur power and area penalty. Wooters et al used only two CLS stages, where the first stage is connected to V DDH through a diode-connected NMOS device [5]. This design avoids intermediate supply voltages, but does not achieve high-speed performance.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient low static-power voltage level shifter

Maroof

Sohail

Shin

2015

IEICE Electron. Express

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Level shifter circuits are necessary parts of modern SoCs, as they interface different voltage domain signals. This paper presents an energyefficient level up shifter capable of converting sub-threshold input signal to higher levels. The proposed design uses the feedback mechanism of a regulated gate cascode to achieve energy efficient operation. Once the desired output level is achieved, large static current does not flow, and static power is further minimized using a transistor stack. Implementing in a 90-nm process, post-layout simulation results show that the proposed level shifter has a propagation delay of 21.2 ns, a total energy-per-transition of only 77.5 fJ, and a static power dissipation of 7.2 nW.

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An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS

Cited by 106 publications

References 11 publications

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

Energy efficient low static-power voltage level shifter

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