An energy-efficient adaptive hybrid cache

Cong,; Gururaj,; Huang, Biao; Liu, Ming; Reinman,; Zou,

doi:10.1109/islped.2011.5993609

Cited by 35 publications

(26 citation statements)

References 15 publications

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“…The potential hit counter increments by one when a hit occurs on a tag entry whose corresponding data block is poweredoff. This is similar to the VTB counters used in [14] [18]. The update of the potential hit counter reuses the same tag array, which does not create extra storage overhead.…”

Section: Dynamic Reconfigurationmentioning

confidence: 96%

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Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Chen¹,

Cong²,

Huang³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-The recent development of non-volatile memory (NVM), such as spin-torque transfer magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of low leakage and high density, provides an energy-efficient alternative to traditional SRAM in cache systems. We propose a novel reconfigurable hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache together with SRAM. RHC can be reconfigured by powering on/off SRAM/NVM arrays in a way-based manner. In this work, we discuss both the architecture and circuit design issues for RHC. Furthermore, we provide hardware-based mechanisms to dynamically reconfigure RHC on-the-fly based on the cache demand. Experimental results on a wide range of benchmarks show that the proposed RHC achieves an average 63%, 48% and 25% energy saving over non-reconfigurable SRAM-based cache, non-reconfigurable hybrid cache, and reconfigurable SRAM-based cache. RHC only introduces at most 4% performance overhead over nonreconfigurable SRAM-based cache and non-reconfigurable hybrid cache.

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Section: Dynamic Reconfigurationmentioning

confidence: 96%

“…Meanwhile, only little performance overhead (less than 4%) are introduced when compared to non-reconfigurable SRAM cache and non-reconfigurable hybrid cache. [18]. The key of these approaches is the dynamic assessment of cache pressure.…”

Section: Introductionmentioning

confidence: 99%

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Chen¹,

Cong²,

Huang³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…Cong et al [32] developed a reconfigurable cache that dynamically remaps scratchpad memory blocks to cache sets with low utilization. This requires additional hardware, as the overhead of managing the remapping process in software would be prohibitive.…”

Section: A Hybrid Cache-scratchpad Architecturesmentioning

confidence: 99%

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

Kluter

Brisk

Charbon

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offers higher bandwidth than interfacing the ISEs the processor's register file, and eliminates the need to allocate separate memories called Architecturally Visible Storage (AVS) that are dedicated to the ISEs, and to ensure coherence between the AVS memories and the processor's data cache. Our results show that Way Stealing is competitive in terms of performance and energy consumption with other techniques that use AVS memories in conjunction with a data cache.

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“…Other works (e.g. [15], [10]) have considered implementing configurable caches in the ASIC domain, which presents different trade-offs than FPGAs.…”

Section: A Memory Architecture In Fpga-based Computingmentioning

confidence: 99%

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Choi

Nam

Canis

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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Abstract-We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator context, we examine the impact of the cache design and its interface. Specifically, we look at how the number of cache ports affects performance when multiple hardware accelerators operate (and access memory) in parallel, and evaluate two different hardware implementations of multi-ported caches using: 1) multi-pumping, and 2) a recently-published approach based on the concept of a livevalue table. Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speedup swings from 0.73× to 6.14×, on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines). Considering both performance and area, the best architecture is found to be a 4-port multi-pump direct-mapped cache with a 16KB cache size and a 128B line size.

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An energy-efficient adaptive hybrid cache

Cited by 35 publications

References 15 publications

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

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