An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes

Mahdi, Ahmed; Kanistras, N.; Paliouras, V.

doi:10.1109/sips.2011.6088997

Cited by 7 publications

(6 citation statements)

References 22 publications

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“…p1 and p2 computational complexity The inverse of the matrix in the equation of p 1 T is not a sparse matrix, thus the computational complexity of the encoder is high. The LDPC decoder operates in linear time, hence it may be difficult to perform low-complexity encoding of these codes [11]. S. Myung et al , in their paper proposed an encoding algorithm for LDPC codes with linearly scaled complexity, based on the principal to choose the matrix φ as the identity matrix or a circulant permutation matrix [26].The encoding procedure of Block-LDPCs is simplified and summarized in equation 10-14 as follows [5].…”

Section: A B T H =mentioning

confidence: 99%

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Mankar¹,

Asutkar²,

Dakhole³

2016

VLSICS

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Section: A B T H =mentioning

confidence: 99%

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Mankar¹,

Asutkar²,

Dakhole³

2016

VLSICS

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“…2, p(1) and p(N-M-1) can be computed by p 1 (0) + λ 0 and p 1 (0) + λ N-M-1 , respectively. The other sub-sequences of the parity bits can be obtained by the forward and backward accumulators according to (10) and (11), respectively. Fig.…”

Section: Proposed High Throughput Encoder Corementioning

confidence: 99%

“…In many literatures, the encoders for QC-LDPC codes were presented [4][5][6][7][8][9][10][11][12][13]. The LDPC encoders presented in [4,5,[7][8][9][10][11] can support various code rates and codeword block lengths. However, these encoders cannot support the high data rate over Gbps.…”

Section: Introductionmentioning

confidence: 99%

7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes

Jung

Chung

Jung

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper proposes a high-throughput encoding process and encoder architecture for quasicyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

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“…In general, while the LDPC decoder can operate in linear time, it may be hard to perform low-complexity encoding of these codes [8].…”

Section: Ii-b Encoding Algorithmmentioning

confidence: 99%

A low-complexity implementation of QC-LDPC encoder in reconfigurable logic

Tzimpragos

Kachris

Soudris

et al. 2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Low Density Parity Check(LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper, a methodology for optimized hardware multiplication by constant matrices in GF(2) is introduced and then applied to the Quasi-Cyclic LDPC encoding algorithm. Taking advantage of the fact that the parity check matrix rarely changes, the signals in many cases are hard-wired into the LUTs and thus the cyclic-shifters and blockmemories conventionally used are eliminated. Therefore, the proposed framework leads to less complex, mapped to reconfigurable logic designs, whereas it combines the performance of hard-wired solutions (high throughput, low latency) and the flexibility of the software and its hardware counterparts. These advantages in terms of hardware savings and throughput prove that the proposed encoder scheme is suitable for high-speed applications, such as long-haul optical transmission, where speed and resources utilization are a major issue.

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An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes

Cited by 7 publications

References 22 publications

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes

A low-complexity implementation of QC-LDPC encoder in reconfigurable logic

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