A low-complexity implementation of QC-LDPC encoder in reconfigurable logic

Abstract

Low Density Parity Check(LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper, a methodology for optimized hardware multiplication by constant matrices in GF(2) is introduced and then applied to the Quasi-Cyclic LDPC encoding algorithm. Taking advantage of the fact that the parity check matrix rarely changes, the signals in many cases are hard-wired into the LUTs and thus the cyclic-shifters and blockmemories conventionally used are eliminated. Therefore, the proposed framework leads to less complex, mapped to reconfigurable logic designs, whereas it combines the performance of hard-wired solutions (high throughput, low latency) and the flexibility of the software and its hardware counterparts. These advantages in terms of hardware savings and throughput prove that the proposed encoder scheme is suitable for high-speed applications, such as long-haul optical transmission, where speed and resources utilization are a major issue.

Automatic implementation of low-complexity QC-LDPC encoders

“…A comparison in terms of throughput and area efficiency between existing solutions and the proposed one ("hard-wired") is provided in [3], proving the latter's superior performance. A performance evaluation of the generated codes in terms of throughput, area and power consumption follows.…”

“…The proposed design is based on the novel hard-wire oriented methodology introduced in [3], leading to efficient QC-LDPC encoders with high throughput and low resources consumption implementations. In general, these methods focus on the optimization of hardware multiplication by constant binary matrices.…”

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

“…Reference [28] proposes a fully parallel LDPC encoder based on reduced complexity XOR trees; it is designed for the IEEE 802.11n standards. Reference [29] introduces a method to improve hardware multiplication based on constant matrices in GF (2); it tries to apply the method to the QC-LDPC encoding algorithm. Reference [30] describes that the throughput of QC-LDPC codes could be improved by trimming the full-base matrix into the requested matrix size.…”

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

“…The LDPC decoder operates in linear time, hence it may be difficult to perform low-complexity encoding of these codes [11]. S. Myung et al , in their paper proposed an encoding algorithm for LDPC codes with linearly scaled complexity, based on the principal to choose the matrix φ as the identity matrix or a circulant permutation matrix [26].The encoding procedure of Block-LDPCs is simplified and summarized in equation 10-14 as follows [5].…”

“…Due to the cyclic structure, they require less memory as compared with the conventional LDPC codes. In addition, QC-LDPC codes also show the high-speed decoding because of the sparseness of its parity check matrix [5]. In all recent wireless communication standards, such as IEEE 802.11n, IEEE 802.11ac, and IEEE 802.16e, the QC-LDPC codes are used as an error correction code [6]- [8].All these wireless communication standards support a very high data rate over hundreds of Mbps.…”