An empirical study of high-order single-bit delta-sigma modulators

Schreier, Richard

doi:10.1109/82.242348

Cited by 289 publications

(188 citation statements)

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“…For example, using this technique one can improve the overall SNR of a 4 th order modulator by 13 dB at an oversampling ratio (OSR) of 32 [5]. Unfortunately, a 4 th order single loop modulator might suffer from stability issues.…”

Section: Mash Versus Smashmentioning

confidence: 99%

Multi-loop efficient sturdy MASH delta-sigma modulators

Maghari

Moon

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards high order multi-loop modulators are discussed and a new multi-loop modulator is presented. This modulator benefits from a MASH architecture in the final loop to preserve stability, while the main loop benefits from relaxed circuit building blocks of the SMASH structure. Extensive simulation results are provided to prove the efficiency of this structure.

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Section: Mash Versus Smashmentioning

confidence: 99%

Multi-loop efficient sturdy MASH delta-sigma modulators

Maghari

Moon

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Such bi-level quantizers were then used to develop the multiplier free analog to digital (A/D) converters, e.g. (Schreier, 1993), to achieve simplest digital hardware circuitry. Based on the bi-level quantizer, the concept of 1-bit processing has been widely investigated in the context of finite-impulse-response (FIR) filters (Kershaw, et al, 1996), infinite-impulse-response (IIR) filters e.g.…”

Section: Delta-sigma (δ∑) Modulation and 1-bit Processing 22mentioning

confidence: 99%

1-Bit processing based model predictive control for fractionated satellite missions

Bai

2014

Acta Astronautica

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In this thesis, a 1-bit processing based Model Predictive Control (OBMPC) structure is proposed for a fractionated satellite attitude control mission. Despite the appealing advantages of the MPC algorithm towards constrained MIMO control applications, implementing the MPC algorithm onboard a small satellite is certainly challenging due to the limited onboard resources. The proposed design is based on the 1-bit processing concept, which takes advantage of the affine relation between the 1-bit state feedback and multi-bit parameters to implement a multiplier free MPC controller.As multipliers are the major power consumer in online optimization, the OBMPC structure is proven to be more efficient in comparison to the conventional MPC implementation in term of power and circuit complexity. The system is in digital control nature, affected by quantization noise introduced by Δ∑ modulators. The stability issues and practical design criteria are also discussed in this work.Some other aspects are considered in this work to complete the control system. Firstly, the implementation of the OBMPC system relies on the 1-bit state feedbacks. Hence, 1-bit sensing components are needed to implement the OBMPC system. While the ∆∑ modulator based Microelectromechanical systems (MEMS) gyroscope is considered in this work, it is possible to implement this concept into other sensing components.Secondly, as the proposed attitude mission is based on the wireless inter-satellite link (ISL), a state estimator is required. However, conventional state estimators will once again introduce multi-bit signals, and compromise the simple, direct implementation of the OBMPC controller. Therefore, the 1-bit state estimator is also designed in this work to satisfy the requirements of the proposed fractionated attitude control mission.The simulation for the OBMPC is based on a 2U CubeSat model in a fractionated satellite structure, in which the payload and actuators are separated from the controller and controlled via the ISL. Matlab simulations and FPGA implementation based performance analysis shows that the OBMPC is feasible for fractionated satellite missions and is advantageous over the conventional MPC controllers. V VI

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“…In order to achieve this SNR with an OSR of only 16, a second-order, multi-bit modu lator with a 3-bit quantizer and zero-optimized NTF [16] was chosen. We started with a NTF for a discrete-time modu lator and mapped it to a CT modulator.…”

Section: A Architecture Selectionmentioning

confidence: 99%

“…The proposed complex CT ADC has the lowest power con sumption (32 mW for complex operation, 15 mW for single real ADC) and smallest active chip area (0.44 mm ) within the medium resolution (10 bit) and wide bandwidth (10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20) state-of-the art ADCs [11]- [14]. The low power consump tion is achieved by choosing a simple second-order 3-bit modu lator, by employing low-noise and high-linearity Gm-C integra tors in the loop filter, and by judicious analog design.…”

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confidence: 99%