An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support

A Novel Signal Processing Coprocessor for <i>n-</i>Dimensional Geometric Algebra Applications

“…The FPGA implementation ran at 20 MHz and in real terms, was found to be much slower than software packages like Gaigen [12] [23] running on typical PC platforms (such as a typical desktop 1.5 GHz machine). The performance differences between software versions of GA and Linear Algebra in solving geometric problems is given in [12] and hardware versions of GA are discussed in [10] [11] [15] [16] [22]. In [10], the hardware was running at a slower clock rate than the software version of the algorithm, which was running on state of the art microprocessors, and therefore to compare the results they needed to be scaled and normalized first.…”

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

“…That is to say, any RRV ⃗ satisfying the dimension constraint (i.e., the number of connections on each side of a PSB( , ) is at most ) is realizable on a PSB ( , ), for ≥ 2 and ∈ even [12]. For example, Figure 13(b) shows a universal PSB (2,6).…”

“…Algorithm 2 removes the switches SW ( , , , ), where , and , belong to the same set of , , and from PSB ( , ), = + + . For example, Figure 13(a) shows a semiuniversal switch block PSB SU (2, 2, 2, 4), which is equal to a universal PSB (2,8) in Figure 13(b) minus some prohibited switches in Figure 13(c). That is to say, a semiuniversal switch block PSB SU ( , , , ) contains a partial topology of the universal switch block PSB ( , ).…”

“…Field Programmable Gate Arrays (FPGA's) [1,2] are now widely used for the implementation of digital circuits and many commercial products. A typical symmetric FPGA, consisting of an array of logic blocks (Ls) that can be connected by general routing resources, is shown in Figure 1.…”

Towards the Optimal Hardware Architecture for Computer Vision

“…They offer a high degree of flexibility and performance to handle many different applications. Most compute-intensive algorithms were migrated to FPGAs: stereo vision (Jin et al, 2010), geometric algebra (Franchini et al, 2009), optical flow (Martineau et al, 2007), object recognition (Meng et al, 2011) or video surveillance (Nair et al, 2005) (Salem et al, 2009) to name some examples. Low and mid-level image processing stages, based on SIMD/MIMD paradigms can be efficiently implemented.…”