A Novel Signal Processing Coprocessor for <i>n-</i>Dimensional Geometric Algebra Applications

Abstract

This paper provides an implementation of a novel signal processing co-processor using a Geometric Algebra technique tailored for fast and complex geometric calculations in multiple dimensions. This is the first hardware implementation of Geometric Algebra to specifically address the issue of scalability to multiple (1 -8) dimensions. This paper presents a detailed description of the implementation, with a particular focus on the techniques of optimization used to improve performance.Results are presented which demonstrate at least 3x performance improvements compared to previously published work.

A Geometric Algebra Co-Processor for Color Edge Detection

“…Table 2 gives a comparison for different dimensions, GA processor performance in MHz, clock cycles, latency and Geometric Operations per Second (GOPS). This also provides a comparison to the GA hardware implementations in [21,23,[25][26][27][28][29][30]. It was found that the proposed hardware is an order of magnitude faster as shown in Table 2 (columns 5-6).…”

“…From an implementation perspective, these functions can also be decomposed into parallelized tasks, each task involving Multiply and Accumulation (MAC) operations, which can map directly to specific hardware. It is already known that significant speed advantages can be gained when GA is implemented in hardware instead of software [21][22][23]. The hardware architecture is discussed in this section, however, a detailed description is beyond the scope of this paper, and the reader is referred to [23] for more information.…”

“…It is already known that significant speed advantages can be gained when GA is implemented in hardware instead of software [21][22][23]. The hardware architecture is discussed in this section, however, a detailed description is beyond the scope of this paper, and the reader is referred to [23] for more information. An important advantage of the architecture is that by having dedicated hardware functions to calculate the GA operations directly, significant efficiencies can be achieved over general-purpose hardware.…”

“…The proposed rotor edge detection hardware architecture consists of an IO interface, control unit, memory unit and a central Geometric Algebra Core [21][22][23] consisting of adder, multiplier, blade logic and a result register ( Figure 2). The architecture supports both single and double precision floating-point numbers, four rounding modes, and exceptions specified by the IEEE 754 standard [24].…”