An embedded DRAM module using a dual sense amplifier architecture in a logic process

Abstract

A dual sense amplifier array architecture (DSSA) amenable to a logic-process-compatible 1T DRAM eliminates the penalty that can be imposed by any two-bank-architecture-based DRAM. The concept is illustrated in Figure 1. Two sense amplifier arrays, SA1 and SA2, are available for one memory array. A bank boundary, a data accessablehnaccessable border of the sense amplifier array, does not exist in the DSAA configuration. Any location o f the memory array can be accessed by both SA1 and SA2. While one sense amplifier array is active, the other is being precharged. Once data on the addressed page (or the X-address) are transferred from the memory array to SA1 (or SA2), the memory array is disconnected from SAL This allows precharging the memory array and preparing the memory array for the next cycle. As long as readwrite operations are performed in the same page, SA1 transacts all the necessary operations without having interaction with the memory array. When readwrite operations are requested in a different page, SA2 responds immediately and services the necessary operations. While SA2 is facilitating the readwrite operation, data in SA1 is written to the memory array after SA2 is disconnected from the memory array.The circuit in Figure 2 shows a physical implementation. Although four sense amplifiers are shown, in one page cycle, only two (either top two or bottom two) participate in reauwrite frondto the memory array. This corresponds to the operation of SA1 and SA2 described above.The sense-amplifier array-select signals are 4 , b l and 4 , b2.One bitline is split into two parts and each is placed separately with a distance of four bitlines pitch. They are then connected by the metal line at the end.To reduce the bitline parasitic capacitance affecting data sensing, only half of the bitline is connected to the sense amplifier. The other half ofthe bitline is disconnected by two of the four select signals, @ a 1 through @ a4. The four control signals are generated from the two LSBs of the X-address.For example, when W1 is selected, @ a1 and cI> a4 remain "high", a2 and @ a3 go "low" and when W2 is selected, @ a 1 and @ a2 remain "high", @ a3 and Q, a4 go "low" and so on.An unique memory cell layout, shown in Figure 3, consisting of four word lines running over a single memory cell, efficiently implements the DSAA architecture. Metal-1 and metal-3 are staggered in the word line layout t o avoid a tight dimension space and geometry. This configuration contributes to a high yield and simplifies the test program. Note that the bitline (metal-2) and the cell plate (poly) are not shown for simplification of the drawing. A 128kb memory array block is also shown as an example of memory cell arrangement. 256b of data come out of the sense amplifier array which consists of 512 sense amplifiers. A 512-row X-decoder is required for the arrangement of 128 memory cells in one column.In commodity DRAM, pass gate subthreshold leakage current is suppressed to the same level as that of the pn junction leakage by applying bias to th...

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