An efficient technique for corner-turn in SAR image reconstruction by improving cache access

Abstract

The performance improvements in SAR(Synthetic Aperture Radar) image reconstruction are one of the key issues in developing practical SAR image processing systems. In order to achieve this goal, we are working to develop an efficient algorithm to process the reconstruction on SMP (Symmetric Multi-processor). In our study, we are focusing on "corner-turn," a subprocess of the reconstruction, which becomes a bottleneck in conventional parallel algorithms because of intensive cache miss hits. We proposed an efficient technique SBCT for parallelizing "corner-turn," reducing cache miss hit. Our new scheme achieves about 25 times speed-up in the parallel "corner-turn" on 8 processors, which contributes to a total performance improvement in SAR image reconstruction of about 20%.

Continuous-Flow Matrix Transposition Using Memories

“…where gcd(n, j ) is the greatest common divisor of n and j . By applying (7) and (8), the read and write addresses for the i -th set of data are calculated as…”

“…To a large extent, this is due to the fact that it is used for the calculation of multidimensional transforms. This makes it a key component for the 2D fast Fourier transform (FFT) in image processing and machine vision [1], multiple-input multipleoutput (MIMO) [2], [3], automotive [4] and synthetic aperture radars [5]- [7]. Likewise, it is required for the 3D FFT in molecular dynamics [8], motion detection [9]; for the 2D discrete cosine transform (DCT) in image compression [10], [11]; for the 2D fast Hartley transform (FHT) in image processing and circular convolution [12], [13]; and for the 3D fast Wavelet transform (FWT) in video encoding [14].…”

“…In a digital system that processes a continuous flow of data [7], [17]- [19], matrix transposition is used to change data in "row by row" order to "column by column" order. The circuit to do this transposition can be based on registers [20] or memories.…”

Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect

“…Its goal is to reorganize data between processing tasks in the coherent processing. In order to increase the locality of memory accesses within any given computational stage of the signal processing chain, it is desirable to reorganize the data in memory according to the dimension that the next processing stage will operate along [31].…”