Continuous-Flow Matrix Transposition Using Memories

Garrido, Mario; Pirsch, P.

doi:10.1109/tcsi.2020.2987736

Cited by 10 publications

(8 citation statements)

References 30 publications

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“…Thus, each memory fits in a 36 Kb BRAM [20] and 4 BRAMs are enough for storing the data. The read and write address of the data memories are generated with a circular counter as in [19].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

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Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

Kaya

Garrido

Takala

2023

IEEE Trans. Circuits Syst. II

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This brief presents a new P -parallel radix-2 memory-based fast Fourier transform (FFT) architecture. The aim of this work is to reduce the number of multiplexers and achieve an efficient memory usage. One advantage of the proposed architecture is that it only needs permutation circuits after the memories, which reduces the multiplexer usage to only one multiplexer per parallel branch. Another advantage is that the architecture calculates the same permutation based on the perfect shuffle at each iteration. Thus, the shuffling circuits do not need to be configured for different iterations. In fact, all the memories require the same read and write addresses, which simplifies the control even further and allows to merge the memories. Along with the hardware efficiency, conflict-free memory access is fulfilled by a circular counter. The FFT has been implemented on a field programmable gate array. Compared to previous approaches, the proposed architecture has the least number of multiplexers and achieves very low area usage.

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“…Thus, each memory fits in a 36 Kb BRAM [20] and 4 BRAMs are enough for storing the data. The read and write address of the data memories are generated with a circular counter as in [19].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

“…It can be proved that σ mem • σ −1 mem = Id. To calculate the permutation σ mem with memories, it must be fulfilled that [19]…”

Section: B Conflict-free Accessmentioning

confidence: 99%

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Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

Kaya

Garrido

Takala

2023

IEEE Trans. Circuits Syst. II

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“…The NPU, driven by the input AER packets, works in an event-triggered approach works. Spike routers translate spikes into weighted latency information by accessing storage and SDRAM (Stankovic and Milenkovic, 2015 ; Goossens et al, 2016 ; Ecco and Ernst, 2017 ; Li et al, 2017 ; Garrido and Pirsch, 2020 ; Benchehida et al, 2022 ).…”

Section: Brain-like Computing Chipsmentioning

confidence: 99%

An overview of brain-like computing: Architecture, applications, and future trends

Xiao²,

Zhu³

et al. 2022

Front. Neurorobot.

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With the development of technology, Moore's law will come to an end, and scientists are trying to find a new way out in brain-like computing. But we still know very little about how the brain works. At the present stage of research, brain-like models are all structured to mimic the brain in order to achieve some of the brain's functions, and then continue to improve the theories and models. This article summarizes the important progress and status of brain-like computing, summarizes the generally accepted and feasible brain-like computing models, introduces, analyzes, and compares the more mature brain-like computing chips, outlines the attempts and challenges of brain-like computing applications at this stage, and looks forward to the future development of brain-like computing. It is hoped that the summarized results will help relevant researchers and practitioners to quickly grasp the research progress in the field of brain-like computing and acquire the application methods and related knowledge in this field.

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“…However, the method was only optimized for multi-dimensional FFT algorithm, was not suitable for spaceborne SAR algorithm. Mario et al [31] optimized the matrix transposition in a continuous flow in a hardware system. However, the method was not suitable for non-squared matrices.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

2021

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With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

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Continuous-Flow Matrix Transposition Using Memories

Cited by 10 publications

References 30 publications

Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage

An overview of brain-like computing: Architecture, applications, and future trends

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

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